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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc10783 DiagnosticPredicate DP(Operand.isGPR64<AArch64::FPR8RegClassID>());
10818 DiagnosticPredicate DP(Operand.isFPRasZPR<AArch64::FPR8RegClassID>());
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc15588 MRI.getRegClass(AArch64::FPR8RegClassID).contains(MI->getOperand(3).getReg()) &&
20783 MRI.getRegClass(AArch64::FPR8RegClassID).contains(MI->getOperand(0).getReg()) &&
20800 MRI.getRegClass(AArch64::FPR8RegClassID).contains(MI->getOperand(0).getReg()) &&
21851 MRI.getRegClass(AArch64::FPR8RegClassID).contains(MI->getOperand(0).getReg()) &&
25253 MRI.getRegClass(AArch64::FPR8RegClassID).contains(MI->getOperand(0).getReg()) &&
25270 MRI.getRegClass(AArch64::FPR8RegClassID).contains(MI->getOperand(0).getReg()) &&
25586 MRI.getRegClass(AArch64::FPR8RegClassID).contains(MI->getOperand(0).getReg()) &&
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc16304 MRI.getRegClass(AArch64::FPR8RegClassID).contains(MI->getOperand(3).getReg()) &&
21499 MRI.getRegClass(AArch64::FPR8RegClassID).contains(MI->getOperand(0).getReg()) &&
21516 MRI.getRegClass(AArch64::FPR8RegClassID).contains(MI->getOperand(0).getReg()) &&
22567 MRI.getRegClass(AArch64::FPR8RegClassID).contains(MI->getOperand(0).getReg()) &&
25969 MRI.getRegClass(AArch64::FPR8RegClassID).contains(MI->getOperand(0).getReg()) &&
25986 MRI.getRegClass(AArch64::FPR8RegClassID).contains(MI->getOperand(0).getReg()) &&
26302 MRI.getRegClass(AArch64::FPR8RegClassID).contains(MI->getOperand(0).getReg()) &&
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc 6461 static const MCOperandInfo OperandInfo60[] = { { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6465 static const MCOperandInfo OperandInfo64[] = { { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6480 static const MCOperandInfo OperandInfo79[] = { { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::PPR_3bRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::ZPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6518 static const MCOperandInfo OperandInfo117[] = { { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::PPR_3bRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::ZPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6518 static const MCOperandInfo OperandInfo117[] = { { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::PPR_3bRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::ZPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6535 static const MCOperandInfo OperandInfo134[] = { { AArch64::ZPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::ZPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::PPR_3bRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6543 static const MCOperandInfo OperandInfo142[] = { { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6646 static const MCOperandInfo OperandInfo245[] = { { AArch64::ZPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::ZPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6711 static const MCOperandInfo OperandInfo310[] = { { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6712 static const MCOperandInfo OperandInfo311[] = { { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6713 static const MCOperandInfo OperandInfo312[] = { { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6714 static const MCOperandInfo OperandInfo313[] = { { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6784 static const MCOperandInfo OperandInfo383[] = { { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6784 static const MCOperandInfo OperandInfo383[] = { { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6785 static const MCOperandInfo OperandInfo384[] = { { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6785 static const MCOperandInfo OperandInfo384[] = { { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6785 static const MCOperandInfo OperandInfo384[] = { { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6796 static const MCOperandInfo OperandInfo395[] = { { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6799 static const MCOperandInfo OperandInfo398[] = { { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6799 static const MCOperandInfo OperandInfo398[] = { { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
6800 static const MCOperandInfo OperandInfo399[] = { { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6819 static const MCOperandInfo OperandInfo418[] = { { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6819 static const MCOperandInfo OperandInfo418[] = { { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6819 static const MCOperandInfo OperandInfo418[] = { { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::FPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
gen/lib/Target/AArch64/AArch64GenRegisterBank.inc 50 (1u << (AArch64::FPR8RegClassID - 0)) |
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc 3437 { FPR8, FPR8Bits, 265, 32, sizeof(FPR8Bits), AArch64::FPR8RegClassID, 1, true },
6894 &AArch64MCRegisterClasses[FPR8RegClassID],
lib/Target/AArch64/AArch64RegisterBankInfo.cpp 228 case AArch64::FPR8RegClassID:
lib/Target/AArch64/AArch64RegisterInfo.cpp 557 case AArch64::FPR8RegClassID: