reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenAsmWriter.inc
17382         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
17408         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
17421         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
17447         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
19117         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
19130         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
19156         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
19211         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
19237         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
19250         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
19276         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
23650         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
23676         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
23689         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
23715         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
24671         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
24684         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
24710         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc
18098         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
18124         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
18137         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
18163         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
19833         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
19846         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
19872         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
19927         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
19953         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
19966         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
19992         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
24366         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
24392         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
24405         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
24431         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
25387         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
25400         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
25426         MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) &&
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc
 6661 static const MCOperandInfo OperandInfo260[] = { { AArch64::DDDDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 6662 static const MCOperandInfo OperandInfo261[] = { { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::DDDDRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
gen/lib/Target/AArch64/AArch64GenRegisterBank.inc
   59     (1u << (AArch64::DDDDRegClassID - 32)) |
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc
 3481   { DDDD, DDDDBits, 270, 32, sizeof(DDDDBits), AArch64::DDDDRegClassID, 1, true },
 7422     &AArch64MCRegisterClasses[DDDDRegClassID],
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
 1083       AArch64::DDRegClassID, AArch64::DDDRegClassID, AArch64::DDDDRegClassID};
lib/Target/AArch64/AArch64RegisterBankInfo.cpp
  236   case AArch64::DDDDRegClassID:
lib/Target/AArch64/AArch64RegisterInfo.cpp
  566   case AArch64::DDDDRegClassID:
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
 1269   else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) ||