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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc16446 { 3314 /* lsr */, AArch64::UBFMWri, Convert__Reg1_0__Reg1_1__Imm0_311_2__imm_95_31, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_Imm0_31 }, },
19263 { 6320 /* ubfm */, AArch64::UBFMWri, Convert__Reg1_0__Reg1_1__Imm0_311_2__Imm0_311_3, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_Imm0_31, MCK_Imm0_31 }, },
19865 { 6893 /* uxtb */, AArch64::UBFMWri, Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_7, AMFBS_None, { MCK_GPR32, MCK_GPR32 }, },
19870 { 6898 /* uxth */, AArch64::UBFMWri, Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_15, AMFBS_None, { MCK_GPR32, MCK_GPR32 }, },
23804 { 3314 /* lsr */, AArch64::UBFMWri, Convert__Reg1_0__Reg1_1__Imm0_311_2__imm_95_31, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_Imm0_31 }, },
26621 { 6320 /* ubfm */, AArch64::UBFMWri, Convert__Reg1_0__Reg1_1__Imm0_311_2__Imm0_311_3, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_Imm0_31, MCK_Imm0_31 }, },
27223 { 6893 /* uxtb */, AArch64::UBFMWri, Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_7, AMFBS_None, { MCK_GPR32, MCK_GPR32 }, },
27228 { 6898 /* uxth */, AArch64::UBFMWri, Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_15, AMFBS_None, { MCK_GPR32, MCK_GPR32 }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc26077 case AArch64::UBFMWri:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc26793 case AArch64::UBFMWri:
gen/lib/Target/AArch64/AArch64GenDAGISel.inc94897 /*215391*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::UBFMWri), 0,
95180 /*215920*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::UBFMWri), 0,
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc37666 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UBFMWri,
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc 9875 case AArch64::UBFMWri: {
lib/Target/AArch64/AArch64FastISel.cpp 4169 {AArch64::UBFMWri, AArch64::UBFMXri}
4290 {AArch64::UBFMWri, AArch64::UBFMXri}
4399 {AArch64::UBFMWri, AArch64::UBFMXri}
4441 Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
4448 Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 1622 Opc = VT == MVT::i32 ? AArch64::UBFMWri : AArch64::UBFMXri;
1693 Opc = AArch64::UBFMWri;
1766 Opc = N->getOpcode() == ISD::SRA ? AArch64::SBFMWri : AArch64::UBFMWri;
1824 case AArch64::UBFMWri:
2046 case AArch64::UBFMWri:
2110 unsigned UBFMOpc = BitWidth == 32 ? AArch64::UBFMWri : AArch64::UBFMXri;
2332 (BFXOpc != AArch64::UBFMWri && VT == MVT::i32))
2420 unsigned ShiftOpc = (VT == MVT::i32) ? AArch64::UBFMWri : AArch64::UBFMXri;
2485 unsigned Opc = (VT == MVT::i32) ? AArch64::UBFMWri : AArch64::UBFMXri;
lib/Target/AArch64/AArch64InstructionSelector.cpp 1221 MIB.buildInstr(Is64Bit ? AArch64::UBFMXri : AArch64::UBFMWri,
1618 I.setDesc(TII.get(SrcSize == 64 ? AArch64::UBFMXri : AArch64::UBFMWri));
2114 ExtI = MIB.buildInstr(IsSigned ? AArch64::SBFMWri : AArch64::UBFMWri,
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp 1027 TII->get(IsStoreXReg ? AArch64::UBFMXri : AArch64::UBFMWri),
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp 74 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) {
123 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
130 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) {