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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc13220 { 665 /* cmp */, AArch64::SUBSXrs, Convert__regXZR__Reg1_0__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64 }, },
13225 { 665 /* cmp */, AArch64::SUBSXrs, Convert__regXZR__Reg1_0__Reg1_1__ArithmeticShifter641_2, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_ArithmeticShifter64 }, },
16740 { 3443 /* negs */, AArch64::SUBSXrs, Convert__Reg1_0__regXZR__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64 }, },
16742 { 3443 /* negs */, AArch64::SUBSXrs, Convert__Reg1_0__regXZR__Reg1_1__ArithmeticShifter641_2, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_ArithmeticShifter64 }, },
19004 { 5976 /* subs */, AArch64::SUBSXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
19009 { 5976 /* subs */, AArch64::SUBSXrs, Convert__Reg1_0__Reg1_1__Reg1_2__ArithmeticShifter641_3, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64, MCK_ArithmeticShifter64 }, },
20578 { 665 /* cmp */, AArch64::SUBSXrs, Convert__regXZR__Reg1_0__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64 }, },
20583 { 665 /* cmp */, AArch64::SUBSXrs, Convert__regXZR__Reg1_0__Reg1_1__ArithmeticShifter641_2, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_ArithmeticShifter64 }, },
24098 { 3443 /* negs */, AArch64::SUBSXrs, Convert__Reg1_0__regXZR__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64 }, },
24100 { 3443 /* negs */, AArch64::SUBSXrs, Convert__Reg1_0__regXZR__Reg1_1__ArithmeticShifter641_2, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_ArithmeticShifter64 }, },
26362 { 5976 /* subs */, AArch64::SUBSXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
26367 { 5976 /* subs */, AArch64::SUBSXrs, Convert__Reg1_0__Reg1_1__Reg1_2__ArithmeticShifter641_3, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64, MCK_ArithmeticShifter64 }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc25831 case AArch64::SUBSXrs:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc26547 case AArch64::SUBSXrs:
gen/lib/Target/AArch64/AArch64GenDAGISel.inc86932 /*200656*/ OPC_MorphNodeTo2, TARGET_VAL(AArch64::SUBSXrs), 0,
93566 /*212886*/ OPC_MorphNodeTo2, TARGET_VAL(AArch64::SUBSXrs), 0,
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc 4493 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSXrs,
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc18038 case AArch64::SUBSXrs:
18377 case AArch64::SUBSXrs:
29776 case AArch64::SUBSXrs:
30115 case AArch64::SUBSXrs:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc15475 case AArch64::SUBSXrs:
lib/Target/AArch64/AArch64AsmPrinter.cpp 314 MCInstBuilder(AArch64::SUBSXrs)
385 MCInstBuilder(AArch64::SUBSXrs)
lib/Target/AArch64/AArch64CondBrTuning.cpp 240 case AArch64::SUBSXrs:
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 286 BuildMI(LoadCmpBB, DL, TII->get(AArch64::SUBSXrs), AArch64::XZR)
294 BuildMI(LoadCmpBB, DL, TII->get(AArch64::SUBSXrs), AArch64::XZR)
447 case AArch64::SUBSXrr: Opcode = AArch64::SUBSXrs; break;
647 AArch64::LDAXRX, AArch64::STLXRX, AArch64::SUBSXrs,
lib/Target/AArch64/AArch64FastISel.cpp 1417 { { AArch64::SUBSWrs, AArch64::SUBSXrs },
5105 CmpOpc = AArch64::SUBSXrs;
lib/Target/AArch64/AArch64InstrInfo.cpp 806 case AArch64::SUBSXrs: {
1002 case AArch64::SUBSXrs:
1126 case AArch64::SUBSXrs:
1127 return MIDefinesZeroReg ? AArch64::SUBSXrs : AArch64::SUBXrs;
1918 return AArch64::SUBSXrs;
lib/Target/AArch64/AArch64MacroFusion.cpp 53 case AArch64::SUBSXrs:
258 case AArch64::SUBSXrs:
335 case AArch64::SUBSXrs:
348 case AArch64::SUBSXrs:
lib/Target/AArch64/AArch64RedundantCopyElimination.cpp 249 case AArch64::SUBSXrs:
lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp 973 case AArch64::SUBSXrs: