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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc14677 { 1825 /* ins */, AArch64::INSvi64lane, Convert__VectorReg1281_0__Tie0_1_1__IndexRange0_11_2__VectorReg1281_3__IndexRange0_11_5, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_d, MCK_IndexRange0_1, MCK_VectorReg128, MCK__DOT_d, MCK_IndexRange0_1 }, },
16601 { 3356 /* mov */, AArch64::INSvi64lane, Convert__VectorReg1281_0__Tie0_1_1__IndexRange0_11_2__VectorReg1281_3__IndexRange0_11_5, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_d, MCK_IndexRange0_1, MCK_VectorReg128, MCK__DOT_d, MCK_IndexRange0_1 }, },
22035 { 1825 /* ins */, AArch64::INSvi64lane, Convert__VectorReg1281_1__Tie0_2_2__IndexRange0_11_2__VectorReg1281_3__IndexRange0_11_4, AMFBS_HasNEON, { MCK__DOT_d, MCK_VectorReg128, MCK_IndexRange0_1, MCK_VectorReg128, MCK_IndexRange0_1 }, },
23937 { 3356 /* mov */, AArch64::INSvi64lane, Convert__VectorReg1281_1__Tie0_2_2__IndexRange0_11_2__VectorReg1281_3__IndexRange0_11_4, AMFBS_HasNEON, { MCK__DOT_d, MCK_VectorReg128, MCK_IndexRange0_1, MCK_VectorReg128, MCK_IndexRange0_1 }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc17226 case AArch64::INSvi64lane:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc17942 case AArch64::INSvi64lane:
gen/lib/Target/AArch64/AArch64GenDAGISel.inc80414 /*187832*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::INSvi64lane), 0,
109337 /*244187*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::INSvi64lane), 0,
109354 /*244241*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::INSvi64lane), 0,
109371 /*244295*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::INSvi64lane), 0,
109388 /*244349*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::INSvi64lane), 0,
109460 /*244533*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::INSvi64lane), 0,
109477 /*244587*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::INSvi64lane), 0,
109494 /*244641*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::INSvi64lane), 0,
109598 /*244835*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::INSvi64lane), 0,
109897 /*245446*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::INSvi64lane), 0,
109908 /*245477*/ OPC_EmitNode1, TARGET_VAL(AArch64::INSvi64lane), 0,
110019 /*245755*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::INSvi64lane), 0,
110034 /*245801*/ OPC_EmitNode1, TARGET_VAL(AArch64::INSvi64lane), 0,
110232 /*246281*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::INSvi64lane), 0,
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc 7343 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane,
7383 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane,
8081 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane,
8121 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane,
8768 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane,
8808 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane,
9424 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane,
35928 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane,
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc10914 case AArch64::INSvi64lane: {
lib/Target/AArch64/AArch64InstructionSelector.cpp 3135 Opc = AArch64::INSvi64lane;