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References

gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc
14679   { 1825 /* ins */, AArch64::INSvi32lane, Convert__VectorReg1281_0__Tie0_1_1__IndexRange0_31_2__VectorReg1281_3__IndexRange0_31_5, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_s, MCK_IndexRange0_3, MCK_VectorReg128, MCK__DOT_s, MCK_IndexRange0_3 }, },
16603   { 3356 /* mov */, AArch64::INSvi32lane, Convert__VectorReg1281_0__Tie0_1_1__IndexRange0_31_2__VectorReg1281_3__IndexRange0_31_5, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_s, MCK_IndexRange0_3, MCK_VectorReg128, MCK__DOT_s, MCK_IndexRange0_3 }, },
22037   { 1825 /* ins */, AArch64::INSvi32lane, Convert__VectorReg1281_1__Tie0_2_2__IndexRange0_31_2__VectorReg1281_3__IndexRange0_31_4, AMFBS_HasNEON, { MCK__DOT_s, MCK_VectorReg128, MCK_IndexRange0_3, MCK_VectorReg128, MCK_IndexRange0_3 }, },
23939   { 3356 /* mov */, AArch64::INSvi32lane, Convert__VectorReg1281_1__Tie0_2_2__IndexRange0_31_2__VectorReg1281_3__IndexRange0_31_4, AMFBS_HasNEON, { MCK__DOT_s, MCK_VectorReg128, MCK_IndexRange0_3, MCK_VectorReg128, MCK_IndexRange0_3 }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc
17202   case AArch64::INSvi32lane:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc
17918   case AArch64::INSvi32lane:
gen/lib/Target/AArch64/AArch64GenDAGISel.inc
80393 /*187794*/        OPC_MorphNodeTo1, TARGET_VAL(AArch64::INSvi32lane), 0,
109574 /*244791*/          OPC_MorphNodeTo1, TARGET_VAL(AArch64::INSvi32lane), 0,
109863 /*245368*/            OPC_MorphNodeTo1, TARGET_VAL(AArch64::INSvi32lane), 0,
109874 /*245399*/            OPC_EmitNode1, TARGET_VAL(AArch64::INSvi32lane), 0,
109977 /*245647*/            OPC_MorphNodeTo1, TARGET_VAL(AArch64::INSvi32lane), 0,
109992 /*245693*/            OPC_EmitNode1, TARGET_VAL(AArch64::INSvi32lane), 0,
110191 /*246168*/          OPC_MorphNodeTo1, TARGET_VAL(AArch64::INSvi32lane), 0,
110208 /*246221*/          OPC_EmitNode1, TARGET_VAL(AArch64::INSvi32lane), 0,
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc
35895         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi32lane,
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc
10992     case AArch64::INSvi32lane: {
lib/Target/AArch64/AArch64InstructionSelector.cpp
 3132       Opc = AArch64::INSvi32lane;