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References

gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc
14678   { 1825 /* ins */, AArch64::INSvi16lane, Convert__VectorReg1281_0__Tie0_1_1__IndexRange0_71_2__VectorReg1281_3__IndexRange0_71_5, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_h, MCK_IndexRange0_7, MCK_VectorReg128, MCK__DOT_h, MCK_IndexRange0_7 }, },
16602   { 3356 /* mov */, AArch64::INSvi16lane, Convert__VectorReg1281_0__Tie0_1_1__IndexRange0_71_2__VectorReg1281_3__IndexRange0_71_5, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_h, MCK_IndexRange0_7, MCK_VectorReg128, MCK__DOT_h, MCK_IndexRange0_7 }, },
22036   { 1825 /* ins */, AArch64::INSvi16lane, Convert__VectorReg1281_1__Tie0_2_2__IndexRange0_71_2__VectorReg1281_3__IndexRange0_71_4, AMFBS_HasNEON, { MCK__DOT_h, MCK_VectorReg128, MCK_IndexRange0_7, MCK_VectorReg128, MCK_IndexRange0_7 }, },
23938   { 3356 /* mov */, AArch64::INSvi16lane, Convert__VectorReg1281_1__Tie0_2_2__IndexRange0_71_2__VectorReg1281_3__IndexRange0_71_4, AMFBS_HasNEON, { MCK__DOT_h, MCK_VectorReg128, MCK_IndexRange0_7, MCK_VectorReg128, MCK_IndexRange0_7 }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc
17178   case AArch64::INSvi16lane:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc
17894   case AArch64::INSvi16lane:
gen/lib/Target/AArch64/AArch64GenDAGISel.inc
80372 /*187756*/        OPC_MorphNodeTo1, TARGET_VAL(AArch64::INSvi16lane), 0,
109550 /*244747*/          OPC_MorphNodeTo1, TARGET_VAL(AArch64::INSvi16lane), 0,
109829 /*245290*/            OPC_MorphNodeTo1, TARGET_VAL(AArch64::INSvi16lane), 0,
109840 /*245321*/            OPC_EmitNode1, TARGET_VAL(AArch64::INSvi16lane), 0,
109935 /*245539*/            OPC_MorphNodeTo1, TARGET_VAL(AArch64::INSvi16lane), 0,
109950 /*245585*/            OPC_EmitNode1, TARGET_VAL(AArch64::INSvi16lane), 0,
110147 /*246050*/          OPC_MorphNodeTo1, TARGET_VAL(AArch64::INSvi16lane), 0,
110167 /*246107*/          OPC_EmitNode1, TARGET_VAL(AArch64::INSvi16lane), 0,
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc
35862         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi16lane,
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc
11031     case AArch64::INSvi16lane: {
lib/Target/AArch64/AArch64InstructionSelector.cpp
 3129       Opc = AArch64::INSvi16lane;