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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc12710 { 25 /* add */, AArch64::ADDWri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sp, MCK_AddSubImm }, },
16517 { 3356 /* mov */, AArch64::ADDWri, Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_0, AMFBS_None, { MCK_GPR32sponly, MCK_GPR32sp }, },
16524 { 3356 /* mov */, AArch64::ADDWri, Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_0, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sponly }, },
18946 { 5924 /* sub */, AArch64::ADDWri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR32sp, MCK_GPR32sp, MCK_AddSubImmNeg }, },
20068 { 25 /* add */, AArch64::ADDWri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sp, MCK_AddSubImm }, },
23875 { 3356 /* mov */, AArch64::ADDWri, Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_0, AMFBS_None, { MCK_GPR32sponly, MCK_GPR32sp }, },
23882 { 3356 /* mov */, AArch64::ADDWri, Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_0, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sponly }, },
26304 { 5924 /* sub */, AArch64::ADDWri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR32sp, MCK_GPR32sp, MCK_AddSubImmNeg }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc14985 case AArch64::ADDWri:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc15701 case AArch64::ADDWri:
gen/lib/Target/AArch64/AArch64GenDAGISel.inc65499 /*159646*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::ADDWri), 0,
65505 /*159659*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::ADDWri), 0,
86894 /*200570*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::ADDWri), 0,
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc 1129 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWri,
1143 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWri,
4114 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWri,
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc18066 case AArch64::ADDWri:
18282 case AArch64::ADDWri:
29804 case AArch64::ADDWri:
30020 case AArch64::ADDWri:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc 9454 case AArch64::ADDWri:
lib/Target/AArch64/AArch64CondBrTuning.cpp 154 case AArch64::ADDWri:
lib/Target/AArch64/AArch64FastISel.cpp 1371 { AArch64::ADDWri, AArch64::ADDXri } },
lib/Target/AArch64/AArch64InstrInfo.cpp 449 case AArch64::ADDWri:
722 case AArch64::ADDWri:
1101 return MIDefinesZeroReg ? AArch64::ADDSWri : AArch64::ADDWri;
1243 case AArch64::ADDWri:
1843 case AArch64::ADDWri:
2488 BuildMI(MBB, I, DL, get(AArch64::ADDWri), DestReg)
3524 case AArch64::ADDWri:
3716 case AArch64::ADDWri:
lib/Target/AArch64/AArch64InstructionSelector.cpp 3151 {AArch64::ADDWrr, AArch64::ADDWri}};
lib/Target/AArch64/AArch64MacroFusion.cpp 77 case AArch64::ADDWri:
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp 4112 case AArch64::ADDWri:
4145 Inst.getOpcode() == AArch64::ADDWri))