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| import("//llvm/utils/TableGen/tablegen.gni")
tablegen("RISCVGenAsmWriter") {
visibility = [ ":MCTargetDesc" ]
args = [ "-gen-asm-writer" ]
td_file = "../RISCV.td"
}
tablegen("RISCVGenInstrInfo") {
visibility = [ ":tablegen" ]
args = [ "-gen-instr-info" ]
td_file = "../RISCV.td"
}
tablegen("RISCVGenMCCodeEmitter") {
visibility = [ ":MCTargetDesc" ]
args = [ "-gen-emitter" ]
td_file = "../RISCV.td"
}
tablegen("RISCVGenRegisterInfo") {
visibility = [ ":tablegen" ]
args = [ "-gen-register-info" ]
td_file = "../RISCV.td"
}
tablegen("RISCVGenSubtargetInfo") {
visibility = [ ":tablegen" ]
args = [ "-gen-subtarget" ]
td_file = "../RISCV.td"
}
# This should contain tablegen targets generating .inc files included
# by other targets. .inc files only used by .cpp files in this directory
# should be in deps on the static_library instead.
group("tablegen") {
visibility = [
":MCTargetDesc",
"../Utils",
]
public_deps = [
":RISCVGenInstrInfo",
":RISCVGenRegisterInfo",
":RISCVGenSubtargetInfo",
]
}
static_library("MCTargetDesc") {
output_name = "LLVMRISCVDesc"
public_deps = [
":tablegen",
]
deps = [
":RISCVGenAsmWriter",
":RISCVGenMCCodeEmitter",
"//llvm/lib/MC",
"//llvm/lib/Support",
"//llvm/lib/Target/RISCV:RISCVGenCompressInstEmitter",
"//llvm/lib/Target/RISCV/Utils",
]
include_dirs = [ ".." ]
sources = [
"RISCVAsmBackend.cpp",
"RISCVELFObjectWriter.cpp",
"RISCVELFStreamer.cpp",
"RISCVInstPrinter.cpp",
"RISCVMCAsmInfo.cpp",
"RISCVMCCodeEmitter.cpp",
"RISCVMCExpr.cpp",
"RISCVMCTargetDesc.cpp",
"RISCVTargetStreamer.cpp",
]
}
|