reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
313 Idx = StringTable.get(""); 317 Idx = StringTable.get(Str); 547 O << StringTable.get(AsmNames[i]) << ", ";utils/TableGen/DFAEmitter.cpp
152 unsigned InfoIdx = Table.get(KV.second.second);
utils/TableGen/InstrInfoEmitter.cpp 577 OS << InstrNames.get(Inst->TheDef->getName()) << "U, ";
utils/TableGen/IntrinsicEmitter.cpp 533 OS << "(1U<<31) | " << LongEncodingTable.get(TypeSig) << ", ";
utils/TableGen/RegisterInfoEmitter.cpp317 OS << PSetsSeqs.get(PSets[i]) << ","; 334 OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx]) 1001 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0 },\n"; 1006 OS << " { " << RegStrings.get(Reg.getName()) << ", " 1007 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i]) 1007 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i]) 1008 << ", " << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", " 1009 << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << ", " 1010 << LaneMaskSeqs.get(RegUnitLaneMasks[i]) << " },\n"; 1078 << RegClassStrings.get(RC.getName()) << ", " 1287 OS << ", VTLists+" << VTSeqs.get(VTs) << " }, // " 1404 << SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n ";