reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
1202 emitSourceFileHeader("Target Register and Register Classes Information", OS); 1204 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; 1205 OS << "#undef GET_REGINFO_TARGET_DESC\n\n"; 1207 OS << "namespace llvm {\n\n"; 1210 OS << "extern const MCRegisterClass " << Target.getName() 1242 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n"; 1243 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other"); 1244 OS << "};\n"; 1247 OS << "\nstatic const char *const SubRegIndexNameTable[] = { \""; 1250 OS << Idx.getName(); 1251 OS << "\", \""; 1253 OS << "\" };\n\n"; 1256 OS << "\nstatic const LaneBitmask SubRegIndexLaneMaskTable[] = {\n " 1259 printMask(OS << " ", Idx.LaneMask); 1260 OS << ", // " << Idx.getName() << '\n'; 1262 OS << " };\n\n"; 1264 OS << "\n"; 1268 OS << "\nstatic const TargetRegisterInfo::RegClassInfo RegClassInfos[]" 1272 OS << " // Mode = " << M << " ("; 1274 OS << "Default"; 1276 OS << CGH.getMode(M).Name; 1277 OS << ")\n"; 1282 OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", " 1287 OS << ", VTLists+" << VTSeqs.get(VTs) << " }, // " 1291 OS << "};\n"; 1294 OS << "\nstatic const TargetRegisterClass *const " 1322 OS << "static const uint32_t " << RC.getName() 1324 printBitVectorAsHex(OS, RC.getSubClasses(), 32); 1335 OS << "\n "; 1336 printBitVectorAsHex(OS, MaskBV, 32); 1337 OS << "// " << Idx.getName(); 1340 OS << "\n};\n\n"; 1343 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n"; 1345 SuperRegIdxSeqs.emit(OS, printSubRegIndex); 1346 OS << "};\n\n"; 1356 OS << "static const TargetRegisterClass *const " 1359 OS << " &" << Super->getQualifiedName() << "RegClass,\n"; 1360 OS << " nullptr\n};\n\n"; 1366 OS << "\nstatic inline unsigned " << RC.getName() 1374 OS << " static const MCPhysReg AltOrder" << oi << "[] = {"; 1376 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]); 1377 OS << " };\n"; 1380 OS << " const MCRegisterClass &MCR = " << Target.getName() 1386 OS << "),\n ArrayRef<MCPhysReg>("; 1388 OS << "),\n makeArrayRef(AltOrder" << oi; 1389 OS << ")\n };\n const unsigned Select = " << RC.getName() 1396 OS << "\nnamespace " << RegisterClasses.front().Namespace 1400 OS << " extern const TargetRegisterClass " << RC.getName() 1405 printMask(OS, RC.LaneMask); 1406 OS << ",\n " << (unsigned)RC.AllocationPriority << ",\n " 1412 OS << "NullRegClasses,\n "; 1414 OS << RC.getName() << "Superclasses,\n "; 1416 OS << "nullptr\n"; 1418 OS << RC.getName() << "GetRawAllocationOrder\n"; 1419 OS << " };\n\n"; 1422 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n"; 1425 OS << "\nnamespace {\n"; 1426 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n"; 1428 OS << " &" << RC.getQualifiedName() << "RegClass,\n"; 1429 OS << " };\n"; 1430 OS << "} // end anonymous namespace\n"; 1434 OS << "\nstatic const TargetRegisterInfoDesc " 1436 OS << " { 0, false },\n"; 1440 OS << " { "; 1441 OS << Reg.CostPerUse << ", " 1445 OS << "};\n"; // End of register descriptors... 1454 emitComposeSubRegIndices(OS, RegBank, ClassName); 1455 emitComposeSubRegIndexLaneMask(OS, RegBank, ClassName); 1460 OS << "const TargetRegisterClass *" << ClassName 1466 OS << " static const uint8_t Table["; 1468 OS << " static const uint16_t Table["; 1471 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n"; 1473 OS << " {\t// " << RC.getName() << "\n"; 1476 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName() 1479 OS << " 0,\t// " << Idx.getName() << "\n"; 1481 OS << " },\n"; 1483 OS << " };\n assert(RC && \"Missing regclass\");\n" 1490 EmitRegUnitPressure(OS, RegBank, ClassName); 1493 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n"; 1494 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n"; 1495 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[];\n"; 1496 OS << "extern const char " << TargetName << "RegStrings[];\n"; 1497 OS << "extern const char " << TargetName << "RegClassStrings[];\n"; 1498 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n"; 1499 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n"; 1500 OS << "extern const MCRegisterInfo::SubRegCoveredBits " 1502 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n"; 1504 EmitRegMappingTables(OS, Regs, true); 1506 OS << ClassName << "::\n" << ClassName 1513 printMask(OS, RegBank.CoveringLanes); 1514 OS << ", RegClassInfos, HwMode) {\n" 1529 EmitRegMapping(OS, Regs, true); 1531 OS << "}\n\n"; 1542 OS << "static const MCPhysReg " << CSRSet->getName() 1545 OS << getQualifiedName((*Regs)[r]) << ", "; 1546 OS << "0 };\n"; 1561 OS << "static const uint32_t " << CSRSet->getName() 1563 printBitVectorAsHex(OS, Covered, 32); 1564 OS << "};\n"; 1566 OS << "\n\n"; 1568 OS << "ArrayRef<const uint32_t *> " << ClassName 1571 OS << " static const uint32_t *const Masks[] = {\n"; 1573 OS << " " << CSRSet->getName() << "_RegMask,\n"; 1574 OS << " };\n"; 1575 OS << " return makeArrayRef(Masks);\n"; 1577 OS << " return None;\n"; 1579 OS << "}\n\n"; 1581 OS << "ArrayRef<const char *> " << ClassName 1584 OS << " static const char *const Names[] = {\n"; 1586 OS << " " << '"' << CSRSet->getName() << '"' << ",\n"; 1587 OS << " };\n"; 1588 OS << " return makeArrayRef(Names);\n"; 1590 OS << " return None;\n"; 1592 OS << "}\n\n"; 1594 OS << "const " << TargetName << "FrameLowering *\n" << TargetName 1600 OS << "} // end namespace llvm\n\n"; 1601 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";