reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
656 OS << " { "; 657 OS << Num << ",\t" << MinOperands << ",\t" 665 if (Inst.isPreISelOpcode) OS << "|(1ULL<<MCID::PreISelOpcode)"; 666 if (Inst.isPseudo) OS << "|(1ULL<<MCID::Pseudo)"; 667 if (Inst.isReturn) OS << "|(1ULL<<MCID::Return)"; 668 if (Inst.isEHScopeReturn) OS << "|(1ULL<<MCID::EHScopeReturn)"; 669 if (Inst.isBranch) OS << "|(1ULL<<MCID::Branch)"; 670 if (Inst.isIndirectBranch) OS << "|(1ULL<<MCID::IndirectBranch)"; 671 if (Inst.isCompare) OS << "|(1ULL<<MCID::Compare)"; 672 if (Inst.isMoveImm) OS << "|(1ULL<<MCID::MoveImm)"; 673 if (Inst.isMoveReg) OS << "|(1ULL<<MCID::MoveReg)"; 674 if (Inst.isBitcast) OS << "|(1ULL<<MCID::Bitcast)"; 675 if (Inst.isAdd) OS << "|(1ULL<<MCID::Add)"; 676 if (Inst.isTrap) OS << "|(1ULL<<MCID::Trap)"; 677 if (Inst.isSelect) OS << "|(1ULL<<MCID::Select)"; 678 if (Inst.isBarrier) OS << "|(1ULL<<MCID::Barrier)"; 679 if (Inst.hasDelaySlot) OS << "|(1ULL<<MCID::DelaySlot)"; 680 if (Inst.isCall) OS << "|(1ULL<<MCID::Call)"; 681 if (Inst.canFoldAsLoad) OS << "|(1ULL<<MCID::FoldableAsLoad)"; 682 if (Inst.mayLoad) OS << "|(1ULL<<MCID::MayLoad)"; 683 if (Inst.mayStore) OS << "|(1ULL<<MCID::MayStore)"; 684 if (Inst.mayRaiseFPException) OS << "|(1ULL<<MCID::MayRaiseFPException)"; 685 if (Inst.isPredicable) OS << "|(1ULL<<MCID::Predicable)"; 686 if (Inst.isConvertibleToThreeAddress) OS << "|(1ULL<<MCID::ConvertibleTo3Addr)"; 687 if (Inst.isCommutable) OS << "|(1ULL<<MCID::Commutable)"; 688 if (Inst.isTerminator) OS << "|(1ULL<<MCID::Terminator)"; 689 if (Inst.isReMaterializable) OS << "|(1ULL<<MCID::Rematerializable)"; 690 if (Inst.isNotDuplicable) OS << "|(1ULL<<MCID::NotDuplicable)"; 691 if (Inst.Operands.hasOptionalDef) OS << "|(1ULL<<MCID::HasOptionalDef)"; 692 if (Inst.usesCustomInserter) OS << "|(1ULL<<MCID::UsesCustomInserter)"; 693 if (Inst.hasPostISelHook) OS << "|(1ULL<<MCID::HasPostISelHook)"; 694 if (Inst.Operands.isVariadic)OS << "|(1ULL<<MCID::Variadic)"; 695 if (Inst.hasSideEffects) OS << "|(1ULL<<MCID::UnmodeledSideEffects)"; 696 if (Inst.isAsCheapAsAMove) OS << "|(1ULL<<MCID::CheapAsAMove)"; 698 OS << "|(1ULL<<MCID::ExtraSrcRegAllocReq)"; 700 OS << "|(1ULL<<MCID::ExtraDefRegAllocReq)"; 701 if (Inst.isRegSequence) OS << "|(1ULL<<MCID::RegSequence)"; 702 if (Inst.isExtractSubreg) OS << "|(1ULL<<MCID::ExtractSubreg)"; 703 if (Inst.isInsertSubreg) OS << "|(1ULL<<MCID::InsertSubreg)"; 704 if (Inst.isConvergent) OS << "|(1ULL<<MCID::Convergent)"; 705 if (Inst.variadicOpsAreDefs) OS << "|(1ULL<<MCID::VariadicOpsAreDefs)"; 719 OS << ", 0x"; 720 OS.write_hex(Value); 721 OS << "ULL, "; 726 OS << "nullptr, "; 728 OS << "ImplicitList" << EmittedLists[UseList] << ", "; 732 OS << "nullptr, "; 734 OS << "ImplicitList" << EmittedLists[DefList] << ", "; 739 OS << "nullptr"; 741 OS << "OperandInfo" << OpInfo.find(OperandInfo)->second; 745 OS << ", -1 " 749 OS << ", " << Target.getInstNamespace() << "::" << Inst.DeprecatedReason 753 OS << ", -1 ,nullptr"; 755 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";