reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
241 const RecVec Decls = Records.getAllDerivedDefinitions("STIPredicateDecl"); 256 const RecVec Defs = 259 RecVec Opcodes = R->getValueAsListOfDefs("Opcodes"); 300 RecVec Classes = Def->getValueAsListOfDefs("Classes"); 306 RecVec Opcodes = EC->getValueAsListOfDefs("Opcodes"); 331 RecVec Classes = Def->getValueAsListOfDefs("Classes"); 338 RecVec Opcodes = EC->getValueAsListOfDefs("Opcodes"); 405 RecVec RV = Records.getAllDerivedDefinitions("STIPredicate"); 441 RecVec MCPredicates = Records.getAllDerivedDefinitions("TIIPredicate"); 465 RecVec Units = Records.getAllDerivedDefinitions("RetireControlUnit"); 480 RecVec Queues = Records.getAllDerivedDefinitions("MemoryQueue"); 524 RecVec ProcRecords = Records.getAllDerivedDefinitions("Processor"); 565 static void scanSchedRW(Record *RWDef, RecVec &RWDefs, 572 RecVec Seq = RWDef->getValueAsListOfDefs("Writes"); 578 RecVec Vars = RWDef->getValueAsListOfDefs("Variants"); 581 RecVec Selected = Variant->getValueAsListOfDefs("Selected"); 598 RecVec SWDefs, SRDefs; 603 RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW"); 614 RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW"); 617 RecVec RWDefs = InstRWDef->getValueAsListOfDefs("OperandReadWrites"); 628 RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW"); 631 RecVec RWDefs = ItinRWDef->getValueAsListOfDefs("OperandReadWrites"); 643 RecVec AliasDefs = Records.getAllDerivedDefinitions("SchedAlias"); 737 RecVec ValidWrites = ReadDef->getValueAsListOfDefs("ValidWrites"); 745 static void splitSchedReadWrites(const RecVec &RWDefs, 746 RecVec &WriteDefs, RecVec &ReadDefs) { 746 RecVec &WriteDefs, RecVec &ReadDefs) { 758 void CodeGenSchedModels::findRWs(const RecVec &RWDefs, 760 RecVec WriteDefs; 761 RecVec ReadDefs; 768 void CodeGenSchedModels::findRWs(const RecVec &RWDefs, IdxVec &RWs, 886 RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW"); 935 const RecVec &RWDefs = SchedClasses[SCIdx].InstRWs; 993 std::string CodeGenSchedModels::createSchedClassName(const RecVec &InstDefs) { 1050 const RecVec *InstDefs = Sets.expand(InstRWDef); 1069 const RecVec &RWDefs = SchedClasses[OldSCIdx].InstRWs; 1071 const RecVec *OrigInstDefs = Sets.expand(RWDefs[0]); 1158 RecVec ItinRecords = ProcModel.ItinsDef->getValueAsListOfDefs("IID"); 1198 RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW"); 1254 RecVec Matched = Rec->getValueAsListOfDefs("MatchedItinClasses"); 1274 const RecVec *InstDefs = Sets.expand(Rec); 1369 RecVec Variants = SchedRW.TheDef->getValueAsListOfDefs("Variants"); 1434 const RecVec VarDefs = SchedRW.TheDef->getValueAsListOfDefs("Variants"); 1454 const RecVec VarDefs = AliasRW.TheDef->getValueAsListOfDefs("Variants"); 1519 RecVec SelectedDefs = VInfo.VarOrSeqDef->getValueAsListOfDefs("Selected"); 1670 RecVec Preds; 1738 bool CodeGenSchedModels::hasSuperGroup(RecVec &SubUnits, CodeGenProcModel &PM) { 1742 RecVec SuperUnits = 1761 RecVec CheckUnits = 1766 RecVec OtherUnits = 1787 RecVec RegisterFileDefs = Records.getAllDerivedDefinitions("RegisterFile"); 1809 RecVec RegisterClasses = RF->getValueAsListOfDefs("RegClasses"); 1854 RecVec WRDefs = Records.getAllDerivedDefinitions("WriteRes"); 1859 RecVec SWRDefs = Records.getAllDerivedDefinitions("SchedWriteRes"); 1864 RecVec RADefs = Records.getAllDerivedDefinitions("ReadAdvance"); 1869 RecVec SRADefs = Records.getAllDerivedDefinitions("SchedReadAdvance"); 1878 RecVec ProcResGroups = Records.getAllDerivedDefinitions("ProcResGroup"); 1960 const RecVec &InstRWs = SC.InstRWs; 1994 RecVec Matched = (*II)->getValueAsListOfDefs("MatchedItinClasses"); 2121 RecVec &WRDefs = ProcModels[PIdx].WriteResDefs; 2127 RecVec ProcResDefs = ProcWriteResDef->getValueAsListOfDefs("ProcResources"); 2137 RecVec &RADefs = ProcModels[PIdx].ReadAdvanceDefs;utils/TableGen/CodeGenSchedule.h
54 RecVec Aliases; 98 RecVec PredTerm; 141 RecVec InstRWs; 225 RecVec ItinDefList; 229 RecVec ItinRWDefs; 233 RecVec UnsupportedFeaturesDefs; 236 RecVec WriteResDefs; 237 RecVec ReadAdvanceDefs; 240 RecVec ProcResourceDefs; 435 RecVec ProcResourceDefs; 436 RecVec ProcResGroups; 557 void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const; 558 void findRWs(const RecVec &RWDefs, IdxVec &RWs, bool IsRead) const; 597 std::string createSchedClassName(const RecVec &InstDefs); 623 bool hasSuperGroup(RecVec &SubUnits, CodeGenProcModel &PM);utils/TableGen/InstrInfoEmitter.cpp
433 RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate"); 482 RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate");utils/TableGen/SubtargetEmitter.cpp
111 void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles, 180 static void printFeatureMask(raw_ostream &OS, RecVec &FeatureList, 235 RecVec ImpliesList = Feature->getValueAsListOfDefs("Implies"); 269 RecVec FeatureList = Processor->getValueAsListOfDefs("Features"); 299 RecVec StageList = ItinData->getValueAsListOfDefs("Stages"); 312 RecVec UnitList = Stage->getValueAsListOfDefs("Units"); 359 RecVec BypassList = ItinData->getValueAsListOfDefs("Bypasses"); 390 RecVec FUs = ProcModel.ItinsDef->getValueAsListOfDefs("FU"); 404 RecVec BPs = ProcModel.ItinsDef->getValueAsListOfDefs("BP"); 629 RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources"); 793 RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources"); 935 void SubtargetEmitter::ExpandProcResources(RecVec &PRVec, 941 RecVec SubResources; 965 RecVec SuperResources = PR->getValueAsListOfDefs("Resources"); 1049 RecVec Matched = I->getValueAsListOfDefs("MatchedItinClasses"); 1104 RecVec PRVec = WriteRes->getValueAsListOfDefs("ProcResources"); 1163 RecVec ValidWrites = ReadAdvance->getValueAsListOfDefs("ValidWrites");