reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

utils/TableGen/AsmMatcherEmitter.cpp

 1216   auto &RegClassList = Target.getRegBank().getRegClasses();

utils/TableGen/CodeGenRegisters.cpp

  941   auto &RegClasses = RegBank.getRegClasses();
  998   auto &RegClasses = RegBank.getRegClasses();
 1595   for (auto &RegClass : RegBank.getRegClasses()) {
 1880   auto &RegClasses = getRegClasses();
 2335   for (const auto &RC : getRegClasses()) {
 2376   for (const auto &RC : getRegClasses()) {

utils/TableGen/CodeGenTarget.cpp

  305   auto &RegClasses = RegBank.getRegClasses();
  366   for (const auto &RC : getRegBank().getRegClasses()) {
  381   for (const auto &RC : getRegBank().getRegClasses())

utils/TableGen/DAGISelMatcherGen.cpp

   29   for (const auto &RC : T.getRegBank().getRegClasses()) {

utils/TableGen/RegisterBankEmitter.cpp

  183   for (const auto &PossibleSubclass : RegisterClassHierarchy.getRegClasses()) {
  200       BitVector BV(RegisterClassHierarchy.getRegClasses().size());
  220         (RegisterClassHierarchy.getRegClasses().size() + 31) / 32);
  252        << RegisterClassHierarchy.getRegClasses().size() << ");\n";

utils/TableGen/RegisterInfoEmitter.cpp

  135   const auto &RegisterClasses = Bank.getRegClasses();
 1029   const auto &RegisterClasses = RegBank.getRegClasses();
 1178   const auto &RegisterClasses = RegBank.getRegClasses();
 1214   const auto &RegisterClasses = RegBank.getRegClasses();
 1625   for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) {
 1644     for (const CodeGenRegisterClass &SRC : RegBank.getRegClasses()) {