reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
9430 outs() << "\t fpu_reserved[0] " << fpu.fpu_reserved[0]; 9431 outs() << " fpu_reserved[1] " << fpu.fpu_reserved[1] << "\n"; 9432 outs() << "\t control: invalid " << fpu.fpu_fcw.invalid; 9433 outs() << " denorm " << fpu.fpu_fcw.denorm; 9434 outs() << " zdiv " << fpu.fpu_fcw.zdiv; 9435 outs() << " ovrfl " << fpu.fpu_fcw.ovrfl; 9436 outs() << " undfl " << fpu.fpu_fcw.undfl; 9437 outs() << " precis " << fpu.fpu_fcw.precis << "\n"; 9439 if (fpu.fpu_fcw.pc == MachO::x86_FP_PREC_24B) 9441 else if (fpu.fpu_fcw.pc == MachO::x86_FP_PREC_53B) 9443 else if (fpu.fpu_fcw.pc == MachO::x86_FP_PREC_64B) 9446 outs() << fpu.fpu_fcw.pc << " "; 9448 if (fpu.fpu_fcw.rc == MachO::x86_FP_RND_NEAR) 9450 else if (fpu.fpu_fcw.rc == MachO::x86_FP_RND_DOWN) 9452 else if (fpu.fpu_fcw.rc == MachO::x86_FP_RND_UP) 9454 else if (fpu.fpu_fcw.rc == MachO::x86_FP_CHOP) 9457 outs() << "\t status: invalid " << fpu.fpu_fsw.invalid; 9458 outs() << " denorm " << fpu.fpu_fsw.denorm; 9459 outs() << " zdiv " << fpu.fpu_fsw.zdiv; 9460 outs() << " ovrfl " << fpu.fpu_fsw.ovrfl; 9461 outs() << " undfl " << fpu.fpu_fsw.undfl; 9462 outs() << " precis " << fpu.fpu_fsw.precis; 9463 outs() << " stkflt " << fpu.fpu_fsw.stkflt << "\n"; 9464 outs() << "\t errsumm " << fpu.fpu_fsw.errsumm; 9465 outs() << " c0 " << fpu.fpu_fsw.c0; 9466 outs() << " c1 " << fpu.fpu_fsw.c1; 9467 outs() << " c2 " << fpu.fpu_fsw.c2; 9468 outs() << " tos " << fpu.fpu_fsw.tos; 9469 outs() << " c3 " << fpu.fpu_fsw.c3; 9470 outs() << " busy " << fpu.fpu_fsw.busy << "\n"; 9471 outs() << "\t fpu_ftw " << format("0x%02" PRIx32, fpu.fpu_ftw); 9472 outs() << " fpu_rsrv1 " << format("0x%02" PRIx32, fpu.fpu_rsrv1); 9473 outs() << " fpu_fop " << format("0x%04" PRIx32, fpu.fpu_fop); 9474 outs() << " fpu_ip " << format("0x%08" PRIx32, fpu.fpu_ip) << "\n"; 9475 outs() << "\t fpu_cs " << format("0x%04" PRIx32, fpu.fpu_cs); 9476 outs() << " fpu_rsrv2 " << format("0x%04" PRIx32, fpu.fpu_rsrv2); 9477 outs() << " fpu_dp " << format("0x%08" PRIx32, fpu.fpu_dp); 9478 outs() << " fpu_ds " << format("0x%04" PRIx32, fpu.fpu_ds) << "\n"; 9479 outs() << "\t fpu_rsrv3 " << format("0x%04" PRIx32, fpu.fpu_rsrv3); 9480 outs() << " fpu_mxcsr " << format("0x%08" PRIx32, fpu.fpu_mxcsr); 9481 outs() << " fpu_mxcsrmask " << format("0x%08" PRIx32, fpu.fpu_mxcsrmask); 9484 Print_mmst_reg(fpu.fpu_stmm0); 9486 Print_mmst_reg(fpu.fpu_stmm1); 9488 Print_mmst_reg(fpu.fpu_stmm2); 9490 Print_mmst_reg(fpu.fpu_stmm3); 9492 Print_mmst_reg(fpu.fpu_stmm4); 9494 Print_mmst_reg(fpu.fpu_stmm5); 9496 Print_mmst_reg(fpu.fpu_stmm6); 9498 Print_mmst_reg(fpu.fpu_stmm7); 9500 Print_xmm_reg(fpu.fpu_xmm0); 9502 Print_xmm_reg(fpu.fpu_xmm1); 9504 Print_xmm_reg(fpu.fpu_xmm2); 9506 Print_xmm_reg(fpu.fpu_xmm3); 9508 Print_xmm_reg(fpu.fpu_xmm4); 9510 Print_xmm_reg(fpu.fpu_xmm5); 9512 Print_xmm_reg(fpu.fpu_xmm6); 9514 Print_xmm_reg(fpu.fpu_xmm7); 9516 Print_xmm_reg(fpu.fpu_xmm8); 9518 Print_xmm_reg(fpu.fpu_xmm9); 9520 Print_xmm_reg(fpu.fpu_xmm10); 9522 Print_xmm_reg(fpu.fpu_xmm11); 9524 Print_xmm_reg(fpu.fpu_xmm12); 9526 Print_xmm_reg(fpu.fpu_xmm13); 9528 Print_xmm_reg(fpu.fpu_xmm14); 9530 Print_xmm_reg(fpu.fpu_xmm15); 9535 outs() << format("%02" PRIx32, fpu.fpu_rsrv4[f * g]) << " "; 9538 outs() << "\t fpu_reserved1 " << format("0x%08" PRIx32, fpu.fpu_reserved1);