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|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
tools/lldb/source/API/SystemInitializerFull.cpp 241 EmulateInstructionMIPS64::Initialize();
338 EmulateInstructionMIPS64::Terminate();
tools/lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp 198 if (EmulateInstructionMIPS64::SupportsEmulatingInstructionsOfTypeStatic(
202 return new EmulateInstructionMIPS64(arch);
665 EmulateInstructionMIPS64::MipsOpcode *
667 static EmulateInstructionMIPS64::MipsOpcode g_opcodes[] = {
669 {"DADDiu", &EmulateInstructionMIPS64::Emulate_DADDiu,
671 {"ADDiu", &EmulateInstructionMIPS64::Emulate_DADDiu,
673 {"SD", &EmulateInstructionMIPS64::Emulate_SD, "SD rt, offset(rs)"},
674 {"LD", &EmulateInstructionMIPS64::Emulate_LD, "LD rt, offset(base)"},
675 {"DSUBU", &EmulateInstructionMIPS64::Emulate_DSUBU_DADDU,
677 {"SUBU", &EmulateInstructionMIPS64::Emulate_DSUBU_DADDU,
679 {"DADDU", &EmulateInstructionMIPS64::Emulate_DSUBU_DADDU,
681 {"ADDU", &EmulateInstructionMIPS64::Emulate_DSUBU_DADDU,
683 {"LUI", &EmulateInstructionMIPS64::Emulate_LUI, "LUI rt, immediate"},
693 {"LB", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
695 {"LBE", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
697 {"LBU", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
699 {"LBUE", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
701 {"LDC1", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
703 {"LDL", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
705 {"LDR", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
707 {"LLD", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
709 {"LDC2", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
711 {"LDXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg,
713 {"LH", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
715 {"LHE", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
717 {"LHU", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
719 {"LHUE", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
721 {"LL", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
723 {"LLE", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
725 {"LUXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg,
727 {"LW", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
729 {"LWC1", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
731 {"LWC2", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
733 {"LWE", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
735 {"LWL", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
737 {"LWLE", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
739 {"LWR", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
741 {"LWRE", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
743 {"LWXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg,
746 {"SB", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
748 {"SBE", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
750 {"SC", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
752 {"SCE", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
754 {"SCD", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
756 {"SDL", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
758 {"SDR", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
760 {"SDC1", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
762 {"SDC2", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
764 {"SDXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg,
766 {"SH", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
768 {"SHE", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
770 {"SUXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg,
772 {"SW", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
774 {"SWC1", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
776 {"SWC2", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
778 {"SWE", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
780 {"SWL", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
782 {"SWLE", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
784 {"SWR", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
786 {"SWRE", &EmulateInstructionMIPS64::Emulate_LDST_Imm,
788 {"SWXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg,
792 {"BEQ", &EmulateInstructionMIPS64::Emulate_BXX_3ops, "BEQ rs,rt,offset"},
793 {"BEQ64", &EmulateInstructionMIPS64::Emulate_BXX_3ops, "BEQ rs,rt,offset"},
794 {"BNE", &EmulateInstructionMIPS64::Emulate_BXX_3ops, "BNE rs,rt,offset"},
795 {"BNE64", &EmulateInstructionMIPS64::Emulate_BXX_3ops, "BNE rs,rt,offset"},
796 {"BEQL", &EmulateInstructionMIPS64::Emulate_BXX_3ops,
798 {"BNEL", &EmulateInstructionMIPS64::Emulate_BXX_3ops,
800 {"BGEZALL", &EmulateInstructionMIPS64::Emulate_Bcond_Link,
802 {"BAL", &EmulateInstructionMIPS64::Emulate_BAL, "BAL offset"},
803 {"BGEZAL", &EmulateInstructionMIPS64::Emulate_Bcond_Link,
805 {"BALC", &EmulateInstructionMIPS64::Emulate_BALC, "BALC offset"},
806 {"BC", &EmulateInstructionMIPS64::Emulate_BC, "BC offset"},
807 {"BGEZ", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BGEZ rs,offset"},
808 {"BGEZ64", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BGEZ rs,offset"},
809 {"BLEZALC", &EmulateInstructionMIPS64::Emulate_Bcond_Link_C,
811 {"BGEZALC", &EmulateInstructionMIPS64::Emulate_Bcond_Link_C,
813 {"BLTZALC", &EmulateInstructionMIPS64::Emulate_Bcond_Link_C,
815 {"BGTZALC", &EmulateInstructionMIPS64::Emulate_Bcond_Link_C,
817 {"BEQZALC", &EmulateInstructionMIPS64::Emulate_Bcond_Link_C,
819 {"BNEZALC", &EmulateInstructionMIPS64::Emulate_Bcond_Link_C,
821 {"BEQC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
823 {"BEQC64", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
825 {"BNEC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
827 {"BNEC64", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
829 {"BLTC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
831 {"BLTC64", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
833 {"BGEC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
835 {"BGEC64", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
837 {"BLTUC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
839 {"BLTUC64", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
841 {"BGEUC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
843 {"BGEUC64", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
845 {"BLTZC", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
847 {"BLTZC64", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
849 {"BLEZC", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
851 {"BLEZC64", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
853 {"BGEZC", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
855 {"BGEZC64", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
857 {"BGTZC", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
859 {"BGTZC64", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
861 {"BEQZC", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
863 {"BEQZC64", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
865 {"BNEZC", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
867 {"BNEZC64", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
869 {"BGEZL", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BGEZL rt,offset"},
870 {"BGTZ", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BGTZ rt,offset"},
871 {"BGTZ64", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BGTZ rt,offset"},
872 {"BGTZL", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BGTZL rt,offset"},
873 {"BLEZ", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BLEZ rt,offset"},
874 {"BLEZ64", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BLEZ rt,offset"},
875 {"BLEZL", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BLEZL rt,offset"},
876 {"BLTZ", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BLTZ rt,offset"},
877 {"BLTZ64", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BLTZ rt,offset"},
878 {"BLTZAL", &EmulateInstructionMIPS64::Emulate_Bcond_Link,
880 {"BLTZALL", &EmulateInstructionMIPS64::Emulate_Bcond_Link,
882 {"BLTZL", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BLTZL rt,offset"},
883 {"BOVC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
885 {"BNVC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
887 {"J", &EmulateInstructionMIPS64::Emulate_J, "J target"},
888 {"JAL", &EmulateInstructionMIPS64::Emulate_JAL, "JAL target"},
889 {"JALX", &EmulateInstructionMIPS64::Emulate_JAL, "JALX target"},
890 {"JALR", &EmulateInstructionMIPS64::Emulate_JALR, "JALR target"},
891 {"JALR64", &EmulateInstructionMIPS64::Emulate_JALR, "JALR target"},
892 {"JALR_HB", &EmulateInstructionMIPS64::Emulate_JALR, "JALR.HB target"},
893 {"JIALC", &EmulateInstructionMIPS64::Emulate_JIALC, "JIALC rt,offset"},
894 {"JIALC64", &EmulateInstructionMIPS64::Emulate_JIALC, "JIALC rt,offset"},
895 {"JIC", &EmulateInstructionMIPS64::Emulate_JIC, "JIC rt,offset"},
896 {"JIC64", &EmulateInstructionMIPS64::Emulate_JIC, "JIC rt,offset"},
897 {"JR", &EmulateInstructionMIPS64::Emulate_JR, "JR target"},
898 {"JR64", &EmulateInstructionMIPS64::Emulate_JR, "JR target"},
899 {"JR_HB", &EmulateInstructionMIPS64::Emulate_JR, "JR.HB target"},
900 {"BC1F", &EmulateInstructionMIPS64::Emulate_FP_branch, "BC1F cc, offset"},
901 {"BC1T", &EmulateInstructionMIPS64::Emulate_FP_branch, "BC1T cc, offset"},
902 {"BC1FL", &EmulateInstructionMIPS64::Emulate_FP_branch,
904 {"BC1TL", &EmulateInstructionMIPS64::Emulate_FP_branch,
906 {"BC1EQZ", &EmulateInstructionMIPS64::Emulate_BC1EQZ,
908 {"BC1NEZ", &EmulateInstructionMIPS64::Emulate_BC1NEZ,
910 {"BC1ANY2F", &EmulateInstructionMIPS64::Emulate_3D_branch,
912 {"BC1ANY2T", &EmulateInstructionMIPS64::Emulate_3D_branch,
914 {"BC1ANY4F", &EmulateInstructionMIPS64::Emulate_3D_branch,
916 {"BC1ANY4T", &EmulateInstructionMIPS64::Emulate_3D_branch,
918 {"BNZ_B", &EmulateInstructionMIPS64::Emulate_BNZB, "BNZ.b wt,s16"},
919 {"BNZ_H", &EmulateInstructionMIPS64::Emulate_BNZH, "BNZ.h wt,s16"},
920 {"BNZ_W", &EmulateInstructionMIPS64::Emulate_BNZW, "BNZ.w wt,s16"},
921 {"BNZ_D", &EmulateInstructionMIPS64::Emulate_BNZD, "BNZ.d wt,s16"},
922 {"BZ_B", &EmulateInstructionMIPS64::Emulate_BZB, "BZ.b wt,s16"},
923 {"BZ_H", &EmulateInstructionMIPS64::Emulate_BZH, "BZ.h wt,s16"},
924 {"BZ_W", &EmulateInstructionMIPS64::Emulate_BZW, "BZ.w wt,s16"},
925 {"BZ_D", &EmulateInstructionMIPS64::Emulate_BZD, "BZ.d wt,s16"},
926 {"BNZ_V", &EmulateInstructionMIPS64::Emulate_BNZV, "BNZ.V wt,s16"},
927 {"BZ_V", &EmulateInstructionMIPS64::Emulate_BZV, "BZ.V wt,s16"},