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| # RUN: llvm-mc -disassemble -triple armv8 -mattr=+db -show-encoding < %s | FileCheck %s
# New v8 ARM instructions
# HLT
0x70 0x00 0x00 0xe1
# CHECK: hlt #0
0x7f 0xff 0x0f 0xe1
# CHECK: hlt #65535
0x59 0xf0 0x7f 0xf5
0x51 0xf0 0x7f 0xf5
0x55 0xf0 0x7f 0xf5
0x5d 0xf0 0x7f 0xf5
# CHECK: dmb ishld
# CHECK: dmb oshld
# CHECK: dmb nshld
# CHECK: dmb ld
0x05 0xf0 0x20 0xe3
# CHECK: sevl
# These are the only coprocessor instructions that remain defined in ARMv8
# (The operations on p10/p11 disassemble into FP/NEON instructions)
0x10 0x0e 0x00 0xee
# CHECK: mcr p14
0x10 0x0f 0x00 0xee
# CHECK: mcr p15
0x10 0x0e 0x10 0xee
# CHECK: mrc p14
0x10 0x0f 0x10 0xee
# CHECK: mrc p15
0x00 0x0e 0x40 0xec
# CHECK: mcrr p14
0x00 0x0f 0x40 0xec
# CHECK: mcrr p15
0x00 0x0e 0x50 0xec
# CHECK: mrrc p14
0x00 0x0f 0x50 0xec
# CHECK: mrrc p15
0x00 0x0e 0x80 0xec
# CHECK: stc p14
0x00 0x0e 0x90 0xec
# CHECK: ldc p14
|