reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
    1
    2
    3
    4
    5
    6
    7
    8
    9
   10
   11
   12
   13
   14
   15
   16
   17
   18
   19
   20
   21
   22
   23
   24
   25
   26
   27
   28
   29
   30
   31
   32
   33
   34
   35
   36
   37
   38
   39
   40
   41
   42
   43
   44
   45
   46
   47
   48
   49
   50
   51
   52
   53
   54
   55
   56
   57
   58
   59
   60
   61
   62
   63
   64
   65
   66
   67
   68
   69
   70
   71
   72
   73
   74
   75
   76
   77
   78
   79
   80
   81
   82
   83
   84
   85
   86
   87
   88
   89
   90
   91
   92
   93
   94
   95
   96
   97
   98
   99
  100
  101
  102
  103
  104
  105
  106
  107
  108
  109
  110
  111
  112
  113
  114
  115
  116
  117
  118
  119
  120
  121
  122
  123
  124
  125
  126
  127
  128
  129
  130
  131
  132
  133
  134
  135
  136
  137
  138
  139
  140
  141
  142
  143
  144
  145
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -O2 -mtriple=x86_64-linux-android -mattr=+mmx \
; RUN:     -enable-legalize-types-checking | FileCheck %s
; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu -mattr=+mmx \
; RUN:     -enable-legalize-types-checking | FileCheck %s

define i32 @TestComp128GT(fp128 %d1, fp128 %d2) {
; CHECK-LABEL: TestComp128GT:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    pushq %rax
; CHECK-NEXT:    .cfi_def_cfa_offset 16
; CHECK-NEXT:    callq __gttf2
; CHECK-NEXT:    xorl %ecx, %ecx
; CHECK-NEXT:    testl %eax, %eax
; CHECK-NEXT:    setg %cl
; CHECK-NEXT:    movl %ecx, %eax
; CHECK-NEXT:    popq %rcx
; CHECK-NEXT:    .cfi_def_cfa_offset 8
; CHECK-NEXT:    retq
entry:
  %cmp = fcmp ogt fp128 %d1, %d2
  %conv = zext i1 %cmp to i32
  ret i32 %conv
}

define i32 @TestComp128GE(fp128 %d1, fp128 %d2) {
; CHECK-LABEL: TestComp128GE:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    pushq %rax
; CHECK-NEXT:    .cfi_def_cfa_offset 16
; CHECK-NEXT:    callq __getf2
; CHECK-NEXT:    xorl %ecx, %ecx
; CHECK-NEXT:    testl %eax, %eax
; CHECK-NEXT:    setns %cl
; CHECK-NEXT:    movl %ecx, %eax
; CHECK-NEXT:    popq %rcx
; CHECK-NEXT:    .cfi_def_cfa_offset 8
; CHECK-NEXT:    retq
entry:
  %cmp = fcmp oge fp128 %d1, %d2
  %conv = zext i1 %cmp to i32
  ret i32 %conv
}

define i32 @TestComp128LT(fp128 %d1, fp128 %d2) {
; CHECK-LABEL: TestComp128LT:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    pushq %rax
; CHECK-NEXT:    .cfi_def_cfa_offset 16
; CHECK-NEXT:    callq __lttf2
; CHECK-NEXT:    xorl %ecx, %ecx
; CHECK-NEXT:    testl %eax, %eax
; CHECK-NEXT:    sets %cl
; CHECK-NEXT:    movl %ecx, %eax
; CHECK-NEXT:    popq %rcx
; CHECK-NEXT:    .cfi_def_cfa_offset 8
; CHECK-NEXT:    retq
entry:
  %cmp = fcmp olt fp128 %d1, %d2
  %conv = zext i1 %cmp to i32
  ret i32 %conv
; FIXME: This used to generate a shrl to move the sign bit of eax into bit 0.
; This no longer happens with fp128 compares being expanded by LegalizeDAG.
; We can add a new DAG combine for X86ISD::CMP/SETCC to restore this.
}

define i32 @TestComp128LE(fp128 %d1, fp128 %d2) {
; CHECK-LABEL: TestComp128LE:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    pushq %rax
; CHECK-NEXT:    .cfi_def_cfa_offset 16
; CHECK-NEXT:    callq __letf2
; CHECK-NEXT:    xorl %ecx, %ecx
; CHECK-NEXT:    testl %eax, %eax
; CHECK-NEXT:    setle %cl
; CHECK-NEXT:    movl %ecx, %eax
; CHECK-NEXT:    popq %rcx
; CHECK-NEXT:    .cfi_def_cfa_offset 8
; CHECK-NEXT:    retq
entry:
  %cmp = fcmp ole fp128 %d1, %d2
  %conv = zext i1 %cmp to i32
  ret i32 %conv
}

define i32 @TestComp128EQ(fp128 %d1, fp128 %d2) {
; CHECK-LABEL: TestComp128EQ:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    pushq %rax
; CHECK-NEXT:    .cfi_def_cfa_offset 16
; CHECK-NEXT:    callq __eqtf2
; CHECK-NEXT:    xorl %ecx, %ecx
; CHECK-NEXT:    testl %eax, %eax
; CHECK-NEXT:    sete %cl
; CHECK-NEXT:    movl %ecx, %eax
; CHECK-NEXT:    popq %rcx
; CHECK-NEXT:    .cfi_def_cfa_offset 8
; CHECK-NEXT:    retq
entry:
  %cmp = fcmp oeq fp128 %d1, %d2
  %conv = zext i1 %cmp to i32
  ret i32 %conv
}

define i32 @TestComp128NE(fp128 %d1, fp128 %d2) {
; CHECK-LABEL: TestComp128NE:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    pushq %rax
; CHECK-NEXT:    .cfi_def_cfa_offset 16
; CHECK-NEXT:    callq __netf2
; CHECK-NEXT:    xorl %ecx, %ecx
; CHECK-NEXT:    testl %eax, %eax
; CHECK-NEXT:    setne %cl
; CHECK-NEXT:    movl %ecx, %eax
; CHECK-NEXT:    popq %rcx
; CHECK-NEXT:    .cfi_def_cfa_offset 8
; CHECK-NEXT:    retq
entry:
  %cmp = fcmp une fp128 %d1, %d2
  %conv = zext i1 %cmp to i32
  ret i32 %conv
}

define fp128 @TestMax(fp128 %x, fp128 %y) {
; CHECK-LABEL: TestMax:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    subq $40, %rsp
; CHECK-NEXT:    .cfi_def_cfa_offset 48
; CHECK-NEXT:    movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT:    movaps %xmm1, (%rsp) # 16-byte Spill
; CHECK-NEXT:    callq __gttf2
; CHECK-NEXT:    movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT:    testl %eax, %eax
; CHECK-NEXT:    jg .LBB6_2
; CHECK-NEXT:  # %bb.1: # %entry
; CHECK-NEXT:    movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT:  .LBB6_2: # %entry
; CHECK-NEXT:    addq $40, %rsp
; CHECK-NEXT:    .cfi_def_cfa_offset 8
; CHECK-NEXT:    retq
entry:
  %cmp = fcmp ogt fp128 %x, %y
  %cond = select i1 %cmp, fp128 %x, fp128 %y
  ret fp128 %cond
}