1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AVX
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AVX512VL
--- |
define void @test_unmerge() {
ret void
}
...
---
name: test_unmerge
#
alignment: 16
legalized: true
regBankSelected: true
#
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
- { id: 2, class: vecr }
#
body: |
bb.1 (%ir-block.0):
; AVX-LABEL: name: test_unmerge
; AVX: [[DEF:%[0-9]+]]:vr256 = IMPLICIT_DEF
; AVX: [[COPY:%[0-9]+]]:vr128 = COPY [[DEF]].sub_xmm
; AVX: [[VEXTRACTF128rr:%[0-9]+]]:vr128 = VEXTRACTF128rr [[DEF]], 1
; AVX: $xmm0 = COPY [[COPY]]
; AVX: $xmm1 = COPY [[VEXTRACTF128rr]]
; AVX: RET 0, implicit $xmm0, implicit $xmm1
; AVX512VL-LABEL: name: test_unmerge
; AVX512VL: [[DEF:%[0-9]+]]:vr256x = IMPLICIT_DEF
; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY [[DEF]].sub_xmm
; AVX512VL: [[VEXTRACTF32x4Z256rr:%[0-9]+]]:vr128x = VEXTRACTF32x4Z256rr [[DEF]], 1
; AVX512VL: $xmm0 = COPY [[COPY]]
; AVX512VL: $xmm1 = COPY [[VEXTRACTF32x4Z256rr]]
; AVX512VL: RET 0, implicit $xmm0, implicit $xmm1
%0(<8 x s32>) = IMPLICIT_DEF
%1(<4 x s32>), %2(<4 x s32>) = G_UNMERGE_VALUES %0(<8 x s32>)
$xmm0 = COPY %1(<4 x s32>)
$xmm1 = COPY %2(<4 x s32>)
RET 0, implicit $xmm0, implicit $xmm1
...
|