1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
| # RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512ALL --check-prefix=AVX512VL
--- |
define i64 @test_sub_i64(i64 %arg1, i64 %arg2) {
%ret = sub i64 %arg1, %arg2
ret i64 %ret
}
define i32 @test_sub_i32(i32 %arg1, i32 %arg2) {
%ret = sub i32 %arg1, %arg2
ret i32 %ret
}
define <4 x i32> @test_sub_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) {
%ret = sub <4 x i32> %arg1, %arg2
ret <4 x i32> %ret
}
define <4 x float> @test_sub_v4f32(<4 x float> %arg1, <4 x float> %arg2) {
%ret = fsub <4 x float> %arg1, %arg2
ret <4 x float> %ret
}
...
---
name: test_sub_i64
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
# ALL: %0:gr64 = COPY $rdi
# ALL-NEXT: %1:gr64 = COPY $rsi
# ALL-NEXT: %2:gr64 = SUB64rr %0, %1
body: |
bb.1 (%ir-block.0):
liveins: $edi, $esi
%0(s64) = COPY $rdi
%1(s64) = COPY $rsi
%2(s64) = G_SUB %0, %1
$rax = COPY %2(s64)
...
---
name: test_sub_i32
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
# ALL: %0:gr32 = COPY $edi
# ALL-NEXT: %1:gr32 = COPY $esi
# ALL-NEXT: %2:gr32 = SUB32rr %0, %1
body: |
bb.1 (%ir-block.0):
liveins: $edi, $esi
%0(s32) = COPY $edi
%1(s32) = COPY $esi
%2(s32) = G_SUB %0, %1
$eax = COPY %2(s32)
...
---
name: test_sub_v4i32
alignment: 16
legalized: true
regBankSelected: true
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
- { id: 2, class: vecr }
# NO_AVX512VL: %0:vr128 = COPY $xmm0
# AVX512VL: %0:vr128x = COPY $xmm0
# NO_AVX512VL: %1:vr128 = COPY $xmm1
# AVX512VL: %1:vr128x = COPY $xmm1
# SSE-NEXT: %2:vr128 = PSUBDrr %0, %1
# AVX-NEXT: %2:vr128 = VPSUBDrr %0, %1
# AVX512F-NEXT: %2:vr128 = VPSUBDrr %0, %1
# AVX512VL-NEXT: %2:vr128x = VPSUBDZ128rr %0, %1
body: |
bb.1 (%ir-block.0):
liveins: $xmm0, $xmm1
%0(<4 x s32>) = COPY $xmm0
%1(<4 x s32>) = COPY $xmm1
%2(<4 x s32>) = G_SUB %0, %1
$xmm0 = COPY %2(<4 x s32>)
RET 0, implicit $xmm0
...
---
name: test_sub_v4f32
alignment: 16
legalized: true
regBankSelected: true
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
- { id: 2, class: vecr }
# NO_AVX512VL: %0:vr128 = COPY $xmm0
# NO_AVX512VL: %1:vr128 = COPY $xmm1
# SSE-NEXT: %2:vr128 = SUBPSrr %0, %1
# AVX-NEXT: %2:vr128 = VSUBPSrr %0, %1
# AVX512F-NEXT: %2:vr128 = VSUBPSrr %0, %1
#
# AVX512VL: %0:vr128x = COPY $xmm0
# AVX512VL: %1:vr128x = COPY $xmm1
# AVX512VL-NEXT: %2:vr128x = VSUBPSZ128rr %0, %1
body: |
bb.1 (%ir-block.0):
liveins: $xmm0, $xmm1
%0(<4 x s32>) = COPY $xmm0
%1(<4 x s32>) = COPY $xmm1
%2(<4 x s32>) = G_FSUB %0, %1
$xmm0 = COPY %2(<4 x s32>)
RET 0, implicit $xmm0
...
|