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| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AVX
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AVX512VL
--- |
define void @test_merge() {
ret void
}
...
---
name: test_merge
#
alignment: 16
legalized: true
regBankSelected: true
#
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
#
body: |
bb.1 (%ir-block.0):
; AVX-LABEL: name: test_merge
; AVX: [[DEF:%[0-9]+]]:vr128 = IMPLICIT_DEF
; AVX: undef %2.sub_xmm:vr256 = COPY [[DEF]]
; AVX: [[VINSERTF128rr:%[0-9]+]]:vr256 = VINSERTF128rr %2, [[DEF]], 1
; AVX: $ymm0 = COPY [[VINSERTF128rr]]
; AVX: RET 0, implicit $ymm0
; AVX512VL-LABEL: name: test_merge
; AVX512VL: [[DEF:%[0-9]+]]:vr128x = IMPLICIT_DEF
; AVX512VL: undef %2.sub_xmm:vr256x = COPY [[DEF]]
; AVX512VL: [[VINSERTF32x4Z256rr:%[0-9]+]]:vr256x = VINSERTF32x4Z256rr %2, [[DEF]], 1
; AVX512VL: $ymm0 = COPY [[VINSERTF32x4Z256rr]]
; AVX512VL: RET 0, implicit $ymm0
%0(<4 x s32>) = IMPLICIT_DEF
%1(<8 x s32>) = G_CONCAT_VECTORS %0(<4 x s32>), %0(<4 x s32>)
$ymm0 = COPY %1(<8 x s32>)
RET 0, implicit $ymm0
...
|