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| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s
--- |
define void @test_mul_i1() { ret void}
define i16 @test_mul_i16(i16 %arg1, i16 %arg2) {
%ret = mul i16 %arg1, %arg2
ret i16 %ret
}
define i32 @test_mul_i32(i32 %arg1, i32 %arg2) {
%ret = mul i32 %arg1, %arg2
ret i32 %ret
}
define i64 @test_mul_i64(i64 %arg1, i64 %arg2) {
%ret = mul i64 %arg1, %arg2
ret i64 %ret
}
...
---
name: test_mul_i1
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
- { id: 2, class: _, preferred-register: '' }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_mul_i1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK: [[MUL:%[0-9]+]]:_(s8) = G_MUL [[TRUNC]], [[TRUNC1]]
; CHECK: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
; CHECK: [[COPY1:%[0-9]+]]:_(s8) = COPY [[MUL]](s8)
; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[COPY1]], [[C]]
; CHECK: G_STORE [[AND]](s8), [[DEF]](p0) :: (store 1)
; CHECK: RET 0
%0(s32) = COPY $edx
%1(s1) = G_TRUNC %0(s32)
%2(s1) = G_MUL %1, %1
%3:_(p0) = G_IMPLICIT_DEF
G_STORE %2, %3 :: (store 1)
RET 0
...
---
name: test_mul_i16
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $edi, $esi
; CHECK-LABEL: name: test_mul_i16
; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY $di
; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY $si
; CHECK: [[MUL:%[0-9]+]]:_(s16) = G_MUL [[COPY]], [[COPY1]]
; CHECK: $ax = COPY [[MUL]](s16)
; CHECK: RET 0, implicit $ax
%0(s16) = COPY $di
%1(s16) = COPY $si
%2(s16) = G_MUL %0, %1
$ax = COPY %2(s16)
RET 0, implicit $ax
...
---
name: test_mul_i32
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $edi, $esi
; CHECK-LABEL: name: test_mul_i32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]]
; CHECK: $eax = COPY [[MUL]](s32)
; CHECK: RET 0, implicit $eax
%0(s32) = COPY $edi
%1(s32) = COPY $esi
%2(s32) = G_MUL %0, %1
$eax = COPY %2(s32)
RET 0, implicit $eax
...
---
name: test_mul_i64
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $rdi, $rsi
; CHECK-LABEL: name: test_mul_i64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi
; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[COPY1]]
; CHECK: $rax = COPY [[MUL]](s64)
; CHECK: RET 0, implicit $rax
%0(s64) = COPY $rdi
%1(s64) = COPY $rsi
%2(s64) = G_MUL %0, %1
$rax = COPY %2(s64)
RET 0, implicit $rax
...
|