1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
| ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
; RUN: -enable-ppc-quad-precision -ppc-vsr-nums-as-vr \
; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s
define void @qpFmadd(fp128* nocapture readonly %a, fp128* nocapture %b,
fp128* nocapture readonly %c, fp128* nocapture %res) {
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* %b, align 16
%2 = load fp128, fp128* %c, align 16
%madd = tail call fp128 @llvm.fmuladd.f128(fp128 %0, fp128 %1, fp128 %2)
store fp128 %madd, fp128* %res, align 16
ret void
; CHECK-LABEL: qpFmadd
; CHECK-NOT: bl fmal
; CHECK-DAG: lxv v[[REG3:[0-9]+]], 0(r3)
; CHECK-DAG: lxv v[[REG4:[0-9]+]], 0(r4)
; CHECK-DAG: lxv v[[REG5:[0-9]+]], 0(r5)
; CHECK: xsmaddqp v[[REG5]], v[[REG3]], v[[REG4]]
; CHECK-NEXT: stxv v[[REG5]], 0(r6)
; CHECK-NEXT: blr
}
declare fp128 @llvm.fmuladd.f128(fp128, fp128, fp128)
; Function Attrs: norecurse nounwind
define void @qpFmadd_02(fp128* nocapture readonly %a,
fp128* nocapture readonly %b,
fp128* nocapture readonly %c, fp128* nocapture %res) {
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* %b, align 16
%2 = load fp128, fp128* %c, align 16
%mul = fmul contract fp128 %1, %2
%add = fadd contract fp128 %0, %mul
store fp128 %add, fp128* %res, align 16
ret void
; CHECK-LABEL: qpFmadd_02
; CHECK-NOT: bl __multf3
; CHECK-DAG: lxv v[[REG3:[0-9]+]], 0(r3)
; CHECK-DAG: lxv v[[REG4:[0-9]+]], 0(r4)
; CHECK-DAG: lxv v[[REG5:[0-9]+]], 0(r5)
; CHECK: xsmaddqp v[[REG3]], v[[REG4]], v[[REG5]]
; CHECK-NEXT: stxv v[[REG3]], 0(r6)
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @qpFmadd_03(fp128* nocapture readonly %a,
fp128* nocapture readonly %b,
fp128* nocapture readonly %c, fp128* nocapture %res) {
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* %b, align 16
%mul = fmul contract fp128 %0, %1
%2 = load fp128, fp128* %c, align 16
%add = fadd contract fp128 %mul, %2
store fp128 %add, fp128* %res, align 16
ret void
; CHECK-LABEL: qpFmadd_03
; CHECK-NOT: bl __multf3
; CHECK-DAG: lxv v[[REG3:[0-9]+]], 0(r3)
; CHECK-DAG: lxv v[[REG4:[0-9]+]], 0(r4)
; CHECK-DAG: lxv v[[REG5:[0-9]+]], 0(r5)
; CHECK: xsmaddqp v[[REG5]], v[[REG3]], v[[REG4]]
; CHECK-NEXT: stxv v[[REG5]], 0(r6)
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @qpFnmadd(fp128* nocapture readonly %a,
fp128* nocapture readonly %b,
fp128* nocapture readonly %c, fp128* nocapture %res) {
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* %b, align 16
%2 = load fp128, fp128* %c, align 16
%mul = fmul contract fp128 %1, %2
%add = fadd contract fp128 %0, %mul
%sub = fsub fp128 0xL00000000000000008000000000000000, %add
store fp128 %sub, fp128* %res, align 16
ret void
; CHECK-LABEL: qpFnmadd
; CHECK-NOT: bl __multf3
; CHECK-DAG: lxv v[[REG3:[0-9]+]], 0(r3)
; CHECK-DAG: lxv v[[REG4:[0-9]+]], 0(r4)
; CHECK-DAG: lxv v[[REG5:[0-9]+]], 0(r5)
; CHECK: xsnmaddqp v[[REG3]], v[[REG4]], v[[REG5]]
; CHECK-NEXT: stxv v[[REG3]], 0(r6)
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @qpFnmadd_02(fp128* nocapture readonly %a,
fp128* nocapture readonly %b,
fp128* nocapture readonly %c, fp128* nocapture %res) {
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* %b, align 16
%mul = fmul contract fp128 %0, %1
%2 = load fp128, fp128* %c, align 16
%add = fadd contract fp128 %mul, %2
%sub = fsub fp128 0xL00000000000000008000000000000000, %add
store fp128 %sub, fp128* %res, align 16
ret void
; CHECK-LABEL: qpFnmadd_02
; CHECK-NOT: bl __multf3
; CHECK-DAG: lxv v[[REG3:[0-9]+]], 0(r3)
; CHECK-DAG: lxv v[[REG4:[0-9]+]], 0(r4)
; CHECK-DAG: lxv v[[REG5:[0-9]+]], 0(r5)
; CHECK: xsnmaddqp v[[REG5]], v[[REG3]], v[[REG4]]
; CHECK-NEXT: stxv v[[REG5]], 0(r6)
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @qpFmsub(fp128* nocapture readonly %a,
fp128* nocapture readonly %b,
fp128* nocapture readonly %c, fp128* nocapture %res) {
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* %b, align 16
%2 = load fp128, fp128* %c, align 16
%mul = fmul contract fp128 %1, %2
%sub = fsub contract fp128 %0, %mul
store fp128 %sub, fp128* %res, align 16
ret void
; CHECK-LABEL: qpFmsub
; CHECK-NOT: bl __multf3
; CHECK-DAG: lxv v[[REG3:[0-9]+]], 0(r3)
; CHECK-DAG: lxv v[[REG4:[0-9]+]], 0(r4)
; CHECK-DAG: lxv v[[REG5:[0-9]+]], 0(r5)
; CHECK: xsnmsubqp v[[REG3]], v[[REG4]], v[[REG5]]
; CHECK-NEXT: stxv v[[REG3]], 0(r6)
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @qpFmsub_02(fp128* nocapture readonly %a,
fp128* nocapture readonly %b,
fp128* nocapture readonly %c, fp128* nocapture %res) {
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* %b, align 16
%mul = fmul contract fp128 %0, %1
%2 = load fp128, fp128* %c, align 16
%sub = fsub contract fp128 %mul, %2
store fp128 %sub, fp128* %res, align 16
ret void
; CHECK-LABEL: qpFmsub_02
; CHECK-NOT: bl __multf3
; CHECK-DAG: lxv v[[REG3:[0-9]+]], 0(r3)
; CHECK-DAG: lxv v[[REG4:[0-9]+]], 0(r4)
; CHECK-DAG: lxv v[[REG5:[0-9]+]], 0(r5)
; CHECK: xsmsubqp v[[REG5]], v[[REG3]], v[[REG4]]
; CHECK-NEXT: stxv v[[REG5]], 0(r6)
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @qpFnmsub(fp128* nocapture readonly %a,
fp128* nocapture readonly %b,
fp128* nocapture readonly %c, fp128* nocapture %res) {
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* %b, align 16
%2 = load fp128, fp128* %c, align 16
%mul = fmul contract fp128 %1, %2
%sub = fsub contract fp128 %0, %mul
%sub1 = fsub fp128 0xL00000000000000008000000000000000, %sub
store fp128 %sub1, fp128* %res, align 16
ret void
; CHECK-LABEL: qpFnmsub
; CHECK-NOT: bl __multf3
; CHECK-DAG: lxv v[[REG3:[0-9]+]], 0(r3)
; CHECK-DAG: lxv v[[REG4:[0-9]+]], 0(r4)
; CHECK-DAG: lxv v[[REG5:[0-9]+]], 0(r5)
; CHECK: xsnegqp v[[REG4]], v[[REG4]]
; CHECK: xsnmaddqp v[[REG3]], v[[REG4]], v[[REG5]]
; CHECK-NEXT: stxv v[[REG3]], 0(r6)
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @qpFnmsub_02(fp128* nocapture readonly %a,
fp128* nocapture readonly %b,
fp128* nocapture readonly %c, fp128* nocapture %res) {
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* %b, align 16
%mul = fmul contract fp128 %0, %1
%2 = load fp128, fp128* %c, align 16
%sub = fsub contract fp128 %mul, %2
%sub1 = fsub fp128 0xL00000000000000008000000000000000, %sub
store fp128 %sub1, fp128* %res, align 16
ret void
; CHECK-LABEL: qpFnmsub_02
; CHECK-NOT: bl __multf3
; CHECK-DAG: lxv v[[REG3:[0-9]+]], 0(r3)
; CHECK-DAG: lxv v[[REG4:[0-9]+]], 0(r4)
; CHECK-DAG: lxv v[[REG5:[0-9]+]], 0(r5)
; CHECK: xsnmsubqp v[[REG5]], v[[REG3]], v[[REG4]]
; CHECK-NEXT: stxv v[[REG5]], 0(r6)
; CHECK-NEXT: blr
}
|