reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
    1
    2
    3
    4
    5
    6
    7
    8
    9
   10
   11
   12
   13
   14
   15
   16
   17
   18
   19
   20
   21
   22
   23
   24
   25
   26
   27
   28
   29
   30
   31
   32
   33
   34
   35
   36
   37
   38
   39
   40
   41
   42
   43
   44
   45
   46
   47
   48
   49
   50
   51
   52
   53
   54
   55
   56
   57
   58
   59
   60
   61
   62
   63
   64
   65
   66
   67
   68
   69
   70
   71
   72
   73
   74
   75
   76
   77
   78
   79
   80
   81
   82
   83
   84
   85
   86
   87
   88
   89
   90
   91
   92
   93
   94
   95
   96
   97
   98
   99
  100
  101
  102
  103
  104
  105
  106
  107
  108
  109
  110
  111
  112
  113
  114
  115
  116
  117
  118
  119
  120
  121
  122
  123
  124
  125
  126
  127
  128
  129
  130
  131
  132
  133
  134
  135
  136
  137
  138
  139
  140
  141
  142
  143
  144
  145
  146
  147
  148
  149
  150
  151
  152
  153
  154
  155
  156
  157
  158
  159
  160
  161
  162
  163
  164
  165
  166
  167
  168
  169
  170
  171
  172
  173
  174
  175
  176
  177
  178
  179
  180
  181
  182
  183
  184
  185
  186
; Test the MSA ctcmsa and cfcmsa intrinsics (which are encoded with the ELM
; instruction format).

; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -verify-machineinstrs < %s | FileCheck %s

define i32 @msa_ir_cfcmsa_test() nounwind {
entry:
  %0 = tail call i32 @llvm.mips.cfcmsa(i32 0)
  ret i32 %0
}

; CHECK: msa_ir_cfcmsa_test:
; CHECK: cfcmsa $[[R1:[0-9]+]], $0
; CHECK: .size msa_ir_cfcmsa_test
;
define i32 @msa_csr_cfcmsa_test() nounwind {
entry:
  %0 = tail call i32 @llvm.mips.cfcmsa(i32 1)
  ret i32 %0
}

; CHECK: msa_csr_cfcmsa_test:
; CHECK: cfcmsa $[[R1:[0-9]+]], $1
; CHECK: .size msa_csr_cfcmsa_test
;
define i32 @msa_access_cfcmsa_test() nounwind {
entry:
  %0 = tail call i32 @llvm.mips.cfcmsa(i32 2)
  ret i32 %0
}

; CHECK: msa_access_cfcmsa_test:
; CHECK: cfcmsa $[[R1:[0-9]+]], $2
; CHECK: .size msa_access_cfcmsa_test
;
define i32 @msa_save_cfcmsa_test() nounwind {
entry:
  %0 = tail call i32 @llvm.mips.cfcmsa(i32 3)
  ret i32 %0
}

; CHECK: msa_save_cfcmsa_test:
; CHECK: cfcmsa $[[R1:[0-9]+]], $3
; CHECK: .size msa_save_cfcmsa_test
;
define i32 @msa_modify_cfcmsa_test() nounwind {
entry:
  %0 = tail call i32 @llvm.mips.cfcmsa(i32 4)
  ret i32 %0
}

; CHECK: msa_modify_cfcmsa_test:
; CHECK: cfcmsa $[[R1:[0-9]+]], $4
; CHECK: .size msa_modify_cfcmsa_test
;
define i32 @msa_request_cfcmsa_test() nounwind {
entry:
  %0 = tail call i32 @llvm.mips.cfcmsa(i32 5)
  ret i32 %0
}

; CHECK: msa_request_cfcmsa_test:
; CHECK: cfcmsa $[[R1:[0-9]+]], $5
; CHECK: .size msa_request_cfcmsa_test
;
define i32 @msa_map_cfcmsa_test() nounwind {
entry:
  %0 = tail call i32 @llvm.mips.cfcmsa(i32 6)
  ret i32 %0
}

; CHECK: msa_map_cfcmsa_test:
; CHECK: cfcmsa $[[R1:[0-9]+]], $6
; CHECK: .size msa_map_cfcmsa_test
;
define i32 @msa_unmap_cfcmsa_test() nounwind {
entry:
  %0 = tail call i32 @llvm.mips.cfcmsa(i32 7)
  ret i32 %0
}

; CHECK: msa_unmap_cfcmsa_test:
; CHECK: cfcmsa $[[R1:[0-9]+]], $7
; CHECK: .size msa_unmap_cfcmsa_test
;
define i32 @msa_invalid_reg_cfcmsa_test() nounwind {
entry:
  %0 = tail call i32 @llvm.mips.cfcmsa(i32 8)
  ret i32 %0
}

; CHECK-LABEL: msa_invalid_reg_cfcmsa_test:
; CHECK: cfcmsa ${{[0-9]+}}, $8
;
define void @msa_ir_ctcmsa_test() nounwind {
entry:
  tail call void @llvm.mips.ctcmsa(i32 0, i32 1)
  ret void
}

; CHECK: msa_ir_ctcmsa_test:
; CHECK: ctcmsa $0
; CHECK: .size msa_ir_ctcmsa_test
;
define void @msa_csr_ctcmsa_test() nounwind {
entry:
  tail call void @llvm.mips.ctcmsa(i32 1, i32 1)
  ret void
}

; CHECK: msa_csr_ctcmsa_test:
; CHECK: ctcmsa $1
; CHECK: .size msa_csr_ctcmsa_test
;
define void @msa_access_ctcmsa_test() nounwind {
entry:
  tail call void @llvm.mips.ctcmsa(i32 2, i32 1)
  ret void
}

; CHECK: msa_access_ctcmsa_test:
; CHECK: ctcmsa $2
; CHECK: .size msa_access_ctcmsa_test
;
define void @msa_save_ctcmsa_test() nounwind {
entry:
  tail call void @llvm.mips.ctcmsa(i32 3, i32 1)
  ret void
}

; CHECK: msa_save_ctcmsa_test:
; CHECK: ctcmsa $3
; CHECK: .size msa_save_ctcmsa_test
;
define void @msa_modify_ctcmsa_test() nounwind {
entry:
  tail call void @llvm.mips.ctcmsa(i32 4, i32 1)
  ret void
}

; CHECK: msa_modify_ctcmsa_test:
; CHECK: ctcmsa $4
; CHECK: .size msa_modify_ctcmsa_test
;
define void @msa_request_ctcmsa_test() nounwind {
entry:
  tail call void @llvm.mips.ctcmsa(i32 5, i32 1)
  ret void
}

; CHECK: msa_request_ctcmsa_test:
; CHECK: ctcmsa $5
; CHECK: .size msa_request_ctcmsa_test
;
define void @msa_map_ctcmsa_test() nounwind {
entry:
  tail call void @llvm.mips.ctcmsa(i32 6, i32 1)
  ret void
}

; CHECK: msa_map_ctcmsa_test:
; CHECK: ctcmsa $6
; CHECK: .size msa_map_ctcmsa_test
;
define void @msa_unmap_ctcmsa_test() nounwind {
entry:
  tail call void @llvm.mips.ctcmsa(i32 7, i32 1)
  ret void
}

; CHECK: msa_unmap_ctcmsa_test:
; CHECK: ctcmsa $7
; CHECK: .size msa_unmap_ctcmsa_test
;
define void @msa_invalid_reg_ctcmsa_test() nounwind {
entry:
  tail call void @llvm.mips.ctcmsa(i32 8, i32 1)
  ret void
}

; CHECK: msa_invalid_reg_ctcmsa_test:
; CHECK: ctcmsa $8
;
declare i32 @llvm.mips.cfcmsa(i32) nounwind
declare void @llvm.mips.ctcmsa(i32, i32) nounwind