reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
    1
    2
    3
    4
    5
    6
    7
    8
    9
   10
   11
   12
   13
   14
   15
   16
   17
   18
   19
   20
   21
   22
   23
   24
   25
   26
   27
   28
   29
   30
   31
   32
   33
   34
   35
   36
   37
   38
   39
   40
   41
   42
   43
   44
   45
   46
   47
   48
   49
   50
   51
   52
   53
   54
   55
   56
   57
   58
   59
   60
   61
   62
   63
   64
   65
   66
   67
   68
   69
   70
   71
   72
   73
   74
   75
   76
   77
   78
   79
   80
   81
   82
   83
   84
   85
   86
   87
   88
   89
   90
   91
   92
   93
   94
   95
   96
   97
   98
   99
  100
  101
  102
  103
  104
  105
  106
  107
  108
  109
  110
  111
  112
  113
  114
  115
  116
  117
  118
  119
  120
  121
  122
  123
  124
  125
  126
  127
  128
  129
  130
  131
  132
  133
  134
  135
  136
  137
  138
  139
  140
  141
  142
  143
  144
  145
  146
  147
  148
  149
  150
  151
  152
  153
  154
  155
  156
  157
  158
  159
  160
  161
  162
  163
  164
  165
  166
  167
  168
  169
  170
  171
  172
  173
  174
  175
  176
  177
  178
  179
  180
  181
  182
  183
  184
  185
  186
  187
  188
  189
  190
  191
  192
  193
  194
  195
  196
  197
  198
  199
  200
  201
  202
  203
  204
  205
  206
  207
  208
  209
  210
  211
  212
  213
  214
  215
  216
  217
  218
  219
  220
  221
  222
  223
  224
  225
  226
  227
  228
  229
  230
  231
  232
  233
  234
  235
  236
  237
  238
  239
  240
  241
  242
  243
  244
  245
  246
  247
  248
  249
  250
  251
  252
  253
  254
  255
  256
  257
  258
  259
  260
  261
  262
  263
  264
  265
  266
  267
  268
  269
  270
  271
  272
  273
  274
  275
  276
  277
  278
  279
  280
  281
  282
  283
  284
  285
  286
  287
  288
  289
  290
  291
  292
  293
  294
  295
  296
  297
  298
  299
  300
  301
  302
  303
  304
  305
  306
  307
  308
  309
  310
  311
  312
  313
  314
  315
  316
  317
  318
  319
  320
  321
  322
  323
  324
  325
  326
  327
  328
  329
  330
  331
  332
  333
  334
  335
  336
  337
  338
  339
  340
  341
  342
  343
  344
  345
  346
  347
  348
  349
  350
  351
  352
  353
  354
  355
  356
  357
  358
  359
  360
  361
  362
  363
  364
  365
  366
  367
  368
  369
  370
  371
  372
  373
  374
  375
  376
  377
  378
  379
  380
  381
  382
  383
  384
  385
  386
  387
  388
  389
  390
  391
  392
  393
  394
  395
  396
  397
  398
  399
  400
  401
  402
  403
  404
  405
  406
  407
  408
  409
  410
  411
  412
  413
  414
  415
  416
  417
  418
  419
  420
  421
  422
  423
  424
  425
  426
  427
  428
  429
  430
  431
  432
  433
  434
  435
  436
  437
  438
  439
  440
  441
  442
  443
  444
  445
  446
  447
  448
  449
  450
  451
; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin -mcpu=cyclone < %s | FileCheck %s

;; Test various conversions.
define zeroext i32 @trunc_(i8 zeroext %a, i16 zeroext %b, i32 %c, i64 %d) nounwind ssp {
entry:
; CHECK-LABEL: trunc_
; CHECK: sub sp, sp, #16
; CHECK: strb w0, [sp, #15]
; CHECK: strh w1, [sp, #12]
; CHECK: str w2, [sp, #8]
; CHECK: str x3, [sp]
; CHECK: ldr x8, [sp]
; CHECK: ; kill: def $w8 killed $w8 killed $x8
; CHECK: str w8, [sp, #8]
; CHECK: ldr w8, [sp, #8]
; CHECK: strh w8, [sp, #12]
; CHECK: ldrh w8, [sp, #12]
; CHECK: strb w8, [sp, #15]
; CHECK: ldrb w0, [sp, #15]
; CHECK: add sp, sp, #16
; CHECK: ret
  %a.addr = alloca i8, align 1
  %b.addr = alloca i16, align 2
  %c.addr = alloca i32, align 4
  %d.addr = alloca i64, align 8
  store i8 %a, i8* %a.addr, align 1
  store i16 %b, i16* %b.addr, align 2
  store i32 %c, i32* %c.addr, align 4
  store i64 %d, i64* %d.addr, align 8
  %tmp = load i64, i64* %d.addr, align 8
  %conv = trunc i64 %tmp to i32
  store i32 %conv, i32* %c.addr, align 4
  %tmp1 = load i32, i32* %c.addr, align 4
  %conv2 = trunc i32 %tmp1 to i16
  store i16 %conv2, i16* %b.addr, align 2
  %tmp3 = load i16, i16* %b.addr, align 2
  %conv4 = trunc i16 %tmp3 to i8
  store i8 %conv4, i8* %a.addr, align 1
  %tmp5 = load i8, i8* %a.addr, align 1
  %conv6 = zext i8 %tmp5 to i32
  ret i32 %conv6
}

define i64 @zext_(i8 zeroext %a, i16 zeroext %b, i32 %c, i64 %d) nounwind ssp {
entry:
; CHECK-LABEL: zext_
; CHECK: sub sp, sp, #16
; CHECK: strb w0, [sp, #15]
; CHECK: strh w1, [sp, #12]
; CHECK: str w2, [sp, #8]
; CHECK: str x3, [sp]
; CHECK: ldrb w8, [sp, #15]
; CHECK: strh w8, [sp, #12]
; CHECK: ldrh w8, [sp, #12]
; CHECK: str w8, [sp, #8]
; CHECK: ldr w8, [sp, #8]
; CHECK: mov x9, x8
; CHECK: str x9, [sp]
; CHECK: ldr x0, [sp]
; CHECK: ret
  %a.addr = alloca i8, align 1
  %b.addr = alloca i16, align 2
  %c.addr = alloca i32, align 4
  %d.addr = alloca i64, align 8
  store i8 %a, i8* %a.addr, align 1
  store i16 %b, i16* %b.addr, align 2
  store i32 %c, i32* %c.addr, align 4
  store i64 %d, i64* %d.addr, align 8
  %tmp = load i8, i8* %a.addr, align 1
  %conv = zext i8 %tmp to i16
  store i16 %conv, i16* %b.addr, align 2
  %tmp1 = load i16, i16* %b.addr, align 2
  %conv2 = zext i16 %tmp1 to i32
  store i32 %conv2, i32* %c.addr, align 4
  %tmp3 = load i32, i32* %c.addr, align 4
  %conv4 = zext i32 %tmp3 to i64
  store i64 %conv4, i64* %d.addr, align 8
  %tmp5 = load i64, i64* %d.addr, align 8
  ret i64 %tmp5
}

define i32 @zext_i1_i32(i1 zeroext %a) nounwind ssp {
entry:
; CHECK-LABEL: zext_i1_i32
; CHECK-NOT:   and w0, w0, #0x1
; CHECK:       ret
  %conv = zext i1 %a to i32
  ret i32 %conv;
}

define i64 @zext_i1_i64(i1 zeroext %a) nounwind ssp {
entry:
; CHECK-LABEL: zext_i1_i64
; CHECK-NOT:   and w0, w0, #0x1
; CHECK:       ret
  %conv = zext i1 %a to i64
  ret i64 %conv;
}

define i64 @sext_(i8 signext %a, i16 signext %b, i32 %c, i64 %d) nounwind ssp {
entry:
; CHECK-LABEL: sext_
; CHECK: sub sp, sp, #16
; CHECK: strb w0, [sp, #15]
; CHECK: strh w1, [sp, #12]
; CHECK: str w2, [sp, #8]
; CHECK: str x3, [sp]
; CHECK: ldrsb w8, [sp, #15]
; CHECK: strh w8, [sp, #12]
; CHECK: ldrsh w8, [sp, #12]
; CHECK: str w8, [sp, #8]
; CHECK: ldrsw x9, [sp, #8]
; CHECK: str x9, [sp]
; CHECK: ldr x0, [sp]
; CHECK: ret
  %a.addr = alloca i8, align 1
  %b.addr = alloca i16, align 2
  %c.addr = alloca i32, align 4
  %d.addr = alloca i64, align 8
  store i8 %a, i8* %a.addr, align 1
  store i16 %b, i16* %b.addr, align 2
  store i32 %c, i32* %c.addr, align 4
  store i64 %d, i64* %d.addr, align 8
  %tmp = load i8, i8* %a.addr, align 1
  %conv = sext i8 %tmp to i16
  store i16 %conv, i16* %b.addr, align 2
  %tmp1 = load i16, i16* %b.addr, align 2
  %conv2 = sext i16 %tmp1 to i32
  store i32 %conv2, i32* %c.addr, align 4
  %tmp3 = load i32, i32* %c.addr, align 4
  %conv4 = sext i32 %tmp3 to i64
  store i64 %conv4, i64* %d.addr, align 8
  %tmp5 = load i64, i64* %d.addr, align 8
  ret i64 %tmp5
}

; Test sext i8 to i64

define zeroext i64 @sext_i8_i64(i8 zeroext %in) {
; CHECK-LABEL: sext_i8_i64:
; CHECK: mov x[[TMP:[0-9]+]], x0
; CHECK: sxtb x0, w[[TMP]]
  %big = sext i8 %in to i64
  ret i64 %big
}

define zeroext i64 @sext_i16_i64(i16 zeroext %in) {
; CHECK-LABEL: sext_i16_i64:
; CHECK: mov x[[TMP:[0-9]+]], x0
; CHECK: sxth x0, w[[TMP]]
  %big = sext i16 %in to i64
  ret i64 %big
}

; Test sext i1 to i32
define i32 @sext_i1_i32(i1 signext %a) nounwind ssp {
entry:
; CHECK-LABEL: sext_i1_i32
; CHECK-NOT:   sbfx w0, w0, #0, #1
; CHECK:       ret
  %conv = sext i1 %a to i32
  ret i32 %conv
}

; Test sext i1 to i16
define signext i16 @sext_i1_i16(i1 %a) nounwind ssp {
entry:
; CHECK-LABEL: sext_i1_i16
; CHECK: sbfx w8, w0, #0, #1
; CHECK-NEXT: sxth	w0, w8
  %conv = sext i1 %a to i16
  ret i16 %conv
}

; Test sext i1 to i8
define signext i8 @sext_i1_i8(i1 %a) nounwind ssp {
entry:
; CHECK-LABEL: sext_i1_i8
; CHECK: sbfx w8, w0, #0, #1
; CHECK-NEXT: sxtb w0, w8
  %conv = sext i1 %a to i8
  ret i8 %conv
}

; Test fpext
define double @fpext_(float %a) nounwind ssp {
entry:
; CHECK-LABEL: fpext_
; CHECK: fcvt d0, s0
  %conv = fpext float %a to double
  ret double %conv
}

; Test fptrunc
define float @fptrunc_(double %a) nounwind ssp {
entry:
; CHECK-LABEL: fptrunc_
; CHECK: fcvt s0, d0
  %conv = fptrunc double %a to float
  ret float %conv
}

; Test fptosi
define i32 @fptosi_ws(float %a) nounwind ssp {
entry:
; CHECK-LABEL: fptosi_ws
; CHECK: fcvtzs w0, s0
  %conv = fptosi float %a to i32
  ret i32 %conv
}

; Test fptosi
define i32 @fptosi_wd(double %a) nounwind ssp {
entry:
; CHECK-LABEL: fptosi_wd
; CHECK: fcvtzs w0, d0
  %conv = fptosi double %a to i32
  ret i32 %conv
}

; Test fptoui
define i32 @fptoui_ws(float %a) nounwind ssp {
entry:
; CHECK-LABEL: fptoui_ws
; CHECK: fcvtzu w0, s0
  %conv = fptoui float %a to i32
  ret i32 %conv
}

; Test fptoui
define i32 @fptoui_wd(double %a) nounwind ssp {
entry:
; CHECK-LABEL: fptoui_wd
; CHECK: fcvtzu w0, d0
  %conv = fptoui double %a to i32
  ret i32 %conv
}

; Test sitofp
define float @sitofp_sw_i1(i1 %a) nounwind ssp {
entry:
; CHECK-LABEL: sitofp_sw_i1
; CHECK: sbfx w8, w0, #0, #1
; CHECK: scvtf s0, w8
  %conv = sitofp i1 %a to float
  ret float %conv
}

; Test sitofp
define float @sitofp_sw_i8(i8 %a) nounwind ssp {
entry:
; CHECK-LABEL: sitofp_sw_i8
; CHECK: sxtb w8, w0
; CHECK: scvtf s0, w8
  %conv = sitofp i8 %a to float
  ret float %conv
}

; Test sitofp
define float @sitofp_sw_i16(i16 %a) nounwind ssp {
entry:
; CHECK-LABEL: sitofp_sw_i16
  %conv = sitofp i16 %a to float
  ret float %conv
}

; Test sitofp
define float @sitofp_sw(i32 %a) nounwind ssp {
entry:
; CHECK-LABEL: sitofp_sw
; CHECK: scvtf s0, w0
  %conv = sitofp i32 %a to float
  ret float %conv
}

; Test sitofp
define float @sitofp_sx(i64 %a) nounwind ssp {
entry:
; CHECK-LABEL: sitofp_sx
; CHECK: scvtf s0, x0
  %conv = sitofp i64 %a to float
  ret float %conv
}

; Test sitofp
define double @sitofp_dw(i32 %a) nounwind ssp {
entry:
; CHECK-LABEL: sitofp_dw
; CHECK: scvtf d0, w0
  %conv = sitofp i32 %a to double
  ret double %conv
}

; Test sitofp
define double @sitofp_dx(i64 %a) nounwind ssp {
entry:
; CHECK-LABEL: sitofp_dx
; CHECK: scvtf d0, x0
  %conv = sitofp i64 %a to double
  ret double %conv
}

; Test uitofp
define float @uitofp_sw_i1(i1 %a) nounwind ssp {
entry:
; CHECK-LABEL: uitofp_sw_i1
; CHECK: and w8, w0, #0x1
; CHECK: ucvtf s0, w8
  %conv = uitofp i1 %a to float
  ret float %conv
}

; Test uitofp
define float @uitofp_sw_i8(i8 %a) nounwind ssp {
entry:
; CHECK-LABEL: uitofp_sw_i8
  %conv = uitofp i8 %a to float
  ret float %conv
}

; Test uitofp
define float @uitofp_sw_i16(i16 %a) nounwind ssp {
entry:
; CHECK-LABEL: uitofp_sw_i16
  %conv = uitofp i16 %a to float
  ret float %conv
}

; Test uitofp
define float @uitofp_sw(i32 %a) nounwind ssp {
entry:
; CHECK-LABEL: uitofp_sw
; CHECK: ucvtf s0, w0
  %conv = uitofp i32 %a to float
  ret float %conv
}

; Test uitofp
define float @uitofp_sx(i64 %a) nounwind ssp {
entry:
; CHECK-LABEL: uitofp_sx
; CHECK: ucvtf s0, x0
  %conv = uitofp i64 %a to float
  ret float %conv
}

; Test uitofp
define double @uitofp_dw(i32 %a) nounwind ssp {
entry:
; CHECK-LABEL: uitofp_dw
; CHECK: ucvtf d0, w0
  %conv = uitofp i32 %a to double
  ret double %conv
}

; Test uitofp
define double @uitofp_dx(i64 %a) nounwind ssp {
entry:
; CHECK-LABEL: uitofp_dx
; CHECK: ucvtf d0, x0
  %conv = uitofp i64 %a to double
  ret double %conv
}

define i32 @i64_trunc_i32(i64 %a) nounwind ssp {
entry:
; CHECK-LABEL: i64_trunc_i32
; CHECK-NOT: mov
; CHECK: ret
  %conv = trunc i64 %a to i32
  ret i32 %conv
}

define zeroext i16 @i64_trunc_i16(i64 %a) nounwind ssp {
entry:
; CHECK-LABEL: i64_trunc_i16
; CHECK: and [[REG2:w[0-9]+]], w0, #0xffff
; CHECK: uxth w0, [[REG2]]
  %conv = trunc i64 %a to i16
  ret i16 %conv
}

define zeroext i8 @i64_trunc_i8(i64 %a) nounwind ssp {
entry:
; CHECK-LABEL: i64_trunc_i8
; CHECK: and [[REG2:w[0-9]+]], w0, #0xff
; CHECK: uxtb w0, [[REG2]]
  %conv = trunc i64 %a to i8
  ret i8 %conv
}

define zeroext i1 @i64_trunc_i1(i64 %a) nounwind ssp {
entry:
; CHECK-LABEL: i64_trunc_i1
; CHECK: and [[REG2:w[0-9]+]], w0, #0x1
; CHECK: and w0, [[REG2]], #0x1
  %conv = trunc i64 %a to i1
  ret i1 %conv
}

; rdar://15101939
define void @stack_trunc() nounwind {
; CHECK-LABEL: stack_trunc
; CHECK: sub  sp, sp, #16
; CHECK: ldr  x[[REG:[0-9]+]], [sp]
; CHECK: and  [[REG3:w[0-9]+]], w[[REG]], #0xff
; CHECK: strb [[REG3]], [sp, #15]
; CHECK: add  sp, sp, #16
  %a = alloca i8, align 1
  %b = alloca i64, align 8
  %c = load i64, i64* %b, align 8
  %d = trunc i64 %c to i8
  store i8 %d, i8* %a, align 1
  ret void
}

define zeroext i64 @zext_i8_i64(i8 zeroext %in) {
; CHECK-LABEL: zext_i8_i64:
; CHECK-NOT:   ubfx x0, {{x[0-9]+}}, #0, #8
; CHECK:       ret
  %big = zext i8 %in to i64
  ret i64 %big
}
define zeroext i64 @zext_i16_i64(i16 zeroext %in) {
; CHECK-LABEL: zext_i16_i64:
; CHECK-NOT:   ubfx x0, {{x[0-9]+}}, #0, #16
; CHECK:       ret
  %big = zext i16 %in to i64
  ret i64 %big
}

define float @bitcast_i32_to_float(i32 %a) {
  %1 = bitcast i32 %a to float
  ret float %1
}

define double @bitcast_i64_to_double(i64 %a) {
  %1 = bitcast i64 %a to double
  ret double %1
}

define i32 @bitcast_float_to_i32(float %a) {
  %1 = bitcast float %a to i32
  ret i32 %1
}

define i64 @bitcast_double_to_i64(double %a) {
  %1 = bitcast double %a to i64
  ret i64 %1
}