1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
define void @implicit_def() { ret void }
define void @implicit_def_copy() { ret void }
...
---
name: implicit_def
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
body: |
bb.0:
; CHECK-LABEL: name: implicit_def
; CHECK: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
; CHECK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[DEF]], [[DEF]]
; CHECK: $w0 = COPY [[ADDWrr]]
%0(s32) = G_IMPLICIT_DEF
%1(s32) = G_ADD %0, %0
$w0 = COPY %1(s32)
...
---
name: implicit_def_copy
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
body: |
bb.0:
; CHECK-LABEL: name: implicit_def_copy
; CHECK: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY [[DEF]]
; CHECK: $w0 = COPY [[COPY]]
%0(s32) = G_IMPLICIT_DEF
%1(s32) = COPY %0(s32)
$w0 = COPY %1(s32)
...
|