reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
    1
    2
    3
    4
    5
    6
    7
    8
    9
   10
   11
   12
   13
   14
   15
   16
   17
   18
   19
   20
   21
   22
   23
   24
   25
   26
   27
   28
   29
   30
   31
   32
   33
   34
   35
   36
   37
   38
   39
   40
   41
   42
   43
   44
   45
   46
   47
   48
   49
   50
   51
   52
   53
   54
   55
   56
   57
   58
   59
   60
   61
   62
   63
   64
   65
   66
   67
   68
   69
   70
   71
   72
   73
   74
   75
   76
   77
   78
   79
   80
   81
   82
   83
   84
   85
   86
   87
   88
   89
   90
   91
   92
   93
   94
   95
   96
   97
   98
   99
  100
  101
  102
  103
  104
  105
  106
  107
  108
  109
  110
  111
  112
  113
  114
  115
  116
  117
  118
  119
  120
  121
  122
  123
  124
  125
  126
  127
  128
  129
  130
  131
  132
  133
  134
  135
  136
  137
  138
  139
  140
  141
  142
  143
  144
  145
  146
  147
  148
  149
  150
  151
  152
  153
  154
  155
  156
  157
  158
  159
  160
  161
  162
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=arm64-unknown-unknown -global-isel -global-isel-abort=1 -O0 -run-pass=legalizer %s -o - | FileCheck %s
--- |
  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
  target triple = "aarch64"

  define i8* @test_simple_alloca(i32 %numelts) {
    %addr = alloca i8, i32 %numelts
    ret i8* %addr
  }

  define i8* @test_aligned_alloca(i32 %numelts) {
    %addr = alloca i8, i32 %numelts, align 32
    ret i8* %addr
  }

  define i128* @test_natural_alloca(i32 %numelts) {
    %addr = alloca i128, i32 %numelts
    ret i128* %addr
  }

...
---
name:            test_simple_alloca
alignment:       4
tracksRegLiveness: true
liveins:
  - { reg: '$w0' }
frameInfo:
  maxAlignment:    1
stack:
  - { id: 0, name: addr, type: variable-sized, alignment: 1 }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $w0

    ; CHECK-LABEL: name: test_simple_alloca
    ; CHECK: liveins: $w0
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
    ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
    ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]
    ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
    ; CHECK: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[MUL]], [[C1]]
    ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
    ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]
    ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $sp
    ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
    ; CHECK: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[PTRTOINT]], [[AND]]
    ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[SUB]](s64)
    ; CHECK: $sp = COPY [[INTTOPTR]](p0)
    ; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY [[INTTOPTR]](p0)
    ; CHECK: $x0 = COPY [[COPY2]](p0)
    ; CHECK: RET_ReallyLR implicit $x0
    %0:_(s32) = COPY $w0
    %3:_(s64) = G_CONSTANT i64 1
    %1:_(s64) = G_ZEXT %0(s32)
    %2:_(s64) = G_MUL %1, %3
    %4:_(s64) = G_CONSTANT i64 15
    %5:_(s64) = nuw G_ADD %2, %4
    %6:_(s64) = G_CONSTANT i64 -16
    %7:_(s64) = G_AND %5, %6
    %8:_(p0) = G_DYN_STACKALLOC %7(s64), 0
    $x0 = COPY %8(p0)
    RET_ReallyLR implicit $x0

...
---
name:            test_aligned_alloca
alignment:       4
tracksRegLiveness: true
liveins:
  - { reg: '$w0' }
frameInfo:
  maxAlignment:    32
stack:
  - { id: 0, name: addr, type: variable-sized, alignment: 32 }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $w0

    ; CHECK-LABEL: name: test_aligned_alloca
    ; CHECK: liveins: $w0
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
    ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
    ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]
    ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
    ; CHECK: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[MUL]], [[C1]]
    ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
    ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]
    ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $sp
    ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
    ; CHECK: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[PTRTOINT]], [[AND]]
    ; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -32
    ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C3]]
    ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND1]](s64)
    ; CHECK: $sp = COPY [[INTTOPTR]](p0)
    ; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY [[INTTOPTR]](p0)
    ; CHECK: $x0 = COPY [[COPY2]](p0)
    ; CHECK: RET_ReallyLR implicit $x0
    %0:_(s32) = COPY $w0
    %3:_(s64) = G_CONSTANT i64 1
    %1:_(s64) = G_ZEXT %0(s32)
    %2:_(s64) = G_MUL %1, %3
    %4:_(s64) = G_CONSTANT i64 15
    %5:_(s64) = nuw G_ADD %2, %4
    %6:_(s64) = G_CONSTANT i64 -16
    %7:_(s64) = G_AND %5, %6
    %8:_(p0) = G_DYN_STACKALLOC %7(s64), 32
    $x0 = COPY %8(p0)
    RET_ReallyLR implicit $x0

...
---
name:            test_natural_alloca
alignment:       4
tracksRegLiveness: true
liveins:
  - { reg: '$w0' }
frameInfo:
  maxAlignment:    1
stack:
  - { id: 0, name: addr, type: variable-sized, alignment: 1 }
machineFunctionInfo: {}
body:             |
  bb.1 (%ir-block.0):
    liveins: $w0

    ; CHECK-LABEL: name: test_natural_alloca
    ; CHECK: liveins: $w0
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
    ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
    ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]
    ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
    ; CHECK: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[MUL]], [[C1]]
    ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
    ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]
    ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $sp
    ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
    ; CHECK: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[PTRTOINT]], [[AND]]
    ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[SUB]](s64)
    ; CHECK: $sp = COPY [[INTTOPTR]](p0)
    ; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY [[INTTOPTR]](p0)
    ; CHECK: $x0 = COPY [[COPY2]](p0)
    ; CHECK: RET_ReallyLR implicit $x0
    %0:_(s32) = COPY $w0
    %3:_(s64) = G_CONSTANT i64 16
    %1:_(s64) = G_ZEXT %0(s32)
    %2:_(s64) = G_MUL %1, %3
    %4:_(s64) = G_CONSTANT i64 15
    %5:_(s64) = nuw G_ADD %2, %4
    %6:_(s64) = G_CONSTANT i64 -16
    %7:_(s64) = G_AND %5, %6
    %8:_(p0) = G_DYN_STACKALLOC %7(s64), 0
    $x0 = COPY %8(p0)
    RET_ReallyLR implicit $x0

...