1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-unknown-unknown -o - -verify-machineinstrs -run-pass=instruction-select %s | FileCheck %s
# PR36345
--- |
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-arm-none-eabi"
; Function Attrs: noinline nounwind optnone
define void @fp16_to_gpr([2 x half], [2 x half]* %addr) {
ret void
}
define void @gpr_to_fp16() {
ret void
}
define void @gpr_to_fp16_physreg() {
ret void
}
...
---
name: fp16_to_gpr
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: gpr }
- { id: 4, class: gpr }
- { id: 5, class: gpr }
- { id: 6, class: gpr }
- { id: 7, class: gpr }
- { id: 8, class: gpr }
- { id: 9, class: gpr }
- { id: 10, class: gpr }
- { id: 11, class: gpr }
- { id: 12, class: gpr }
body: |
bb.1 (%ir-block.1):
liveins: $h0, $h1, $x0
; CHECK-LABEL: name: fp16_to_gpr
; CHECK: liveins: $h0, $h1, $x0
; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
; CHECK: [[COPY1:%[0-9]+]]:fpr16 = COPY $h1
; CHECK: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub
; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]]
; CHECK: [[BFMWri:%[0-9]+]]:gpr32 = BFMWri [[DEF]], [[COPY2]], 0, 15
; CHECK: [[SUBREG_TO_REG1:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub
; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG1]]
; CHECK: [[BFMWri1:%[0-9]+]]:gpr32 = BFMWri [[BFMWri]], [[COPY3]], 16, 15
; CHECK: [[COPY4:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: STRWui [[BFMWri1]], [[COPY4]], 0 :: (store 4 into %ir.addr, align 2)
; CHECK: RET_ReallyLR
%1:fpr(s16) = COPY $h0
%2:fpr(s16) = COPY $h1
%3:gpr(s32) = G_IMPLICIT_DEF
%11:gpr(s16) = COPY %1(s16)
%4:gpr(s32) = G_INSERT %3, %11(s16), 0
%12:gpr(s16) = COPY %2(s16)
%5:gpr(s32) = G_INSERT %4, %12(s16), 16
%0:gpr(s32) = COPY %5(s32)
%6:gpr(p0) = COPY $x0
G_STORE %0(s32), %6(p0) :: (store 4 into %ir.addr, align 2)
RET_ReallyLR
...
---
name: gpr_to_fp16
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: fpr }
body: |
bb.1 (%ir-block.0):
liveins: $w0
; CHECK-LABEL: name: gpr_to_fp16
; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]]
; CHECK: [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub
; CHECK: $h0 = COPY [[COPY2]]
; CHECK: RET_ReallyLR implicit $h0
%0:gpr(s32) = COPY $w0
%1:gpr(s16) = G_TRUNC %0(s32)
%2:fpr(s16) = COPY %1(s16)
$h0 = COPY %2(s16)
RET_ReallyLR implicit $h0
...
---
name: gpr_to_fp16_physreg
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
body: |
bb.1 (%ir-block.0):
liveins: $w0
; CHECK-LABEL: name: gpr_to_fp16_physreg
; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]]
; CHECK: [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub
; CHECK: $h0 = COPY [[COPY2]]
; CHECK: RET_ReallyLR implicit $h0
%0:gpr(s32) = COPY $w0
%1:gpr(s16) = G_TRUNC %0(s32)
$h0 = COPY %1(s16)
RET_ReallyLR implicit $h0
...
|