reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
1838 if (MI->getAsmPrinterFlags() & X86::AC_EVEX_2_VEX) 1842 switch (MI->getOpcode()) { 1854 Register Reg = MI->getOperand(0).getReg(); 1889 return LowerTlsAddr(MCInstLowering, *MI); 1899 int64_t Disp = MI->getOperand(1 + X86::AddrDisp).getImm(); 1901 Register Reg = MI->getOperand(0).getReg(); 1909 auto Op = MCInstLowering.LowerMachineOperand(MI, MI->getOperand(1 + i)); 1909 auto Op = MCInstLowering.LowerMachineOperand(MI, MI->getOperand(1 + i)); 1921 auto Op = MCInstLowering.LowerMachineOperand(MI, MI->getOperand(1 + i)); 1921 auto Op = MCInstLowering.LowerMachineOperand(MI, MI->getOperand(1 + i)); 1930 int64_t Disp = MI->getOperand(X86::AddrDisp).getImm(); 1932 Register Reg = MI->getOperand(X86::AddrNumOperands).getReg(); 1939 MIB.addOperand(MCInstLowering.LowerMachineOperand(MI, MI->getOperand(i)).getValue()); 1939 MIB.addOperand(MCInstLowering.LowerMachineOperand(MI, MI->getOperand(i)).getValue()); 1949 auto Op = MCInstLowering.LowerMachineOperand(MI, MI->getOperand(0 + i)); 1949 auto Op = MCInstLowering.LowerMachineOperand(MI, MI->getOperand(0 + i)); 1992 MCInstBuilder(X86::POP32r).addReg(MI->getOperand(0).getReg())); 2002 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS) 2016 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2)); 2027 .addReg(MI->getOperand(0).getReg()) 2028 .addReg(MI->getOperand(1).getReg()) 2033 return LowerSTATEPOINT(*MI, MCInstLowering); 2036 return LowerFAULTING_OP(*MI, MCInstLowering); 2039 return LowerFENTRY_CALL(*MI, MCInstLowering); 2042 return LowerPATCHABLE_OP(*MI, MCInstLowering); 2045 return LowerSTACKMAP(*MI); 2048 return LowerPATCHPOINT(*MI, MCInstLowering); 2051 return LowerPATCHABLE_FUNCTION_ENTER(*MI, MCInstLowering); 2054 return LowerPATCHABLE_RET(*MI, MCInstLowering); 2057 return LowerPATCHABLE_TAIL_CALL(*MI, MCInstLowering); 2060 return LowerPATCHABLE_EVENT_CALL(*MI, MCInstLowering); 2063 return LowerPATCHABLE_TYPED_EVENT_CALL(*MI, MCInstLowering); 2084 EmitSEHInstruction(MI); 2089 MachineBasicBlock::const_iterator MBBI(MI); 2123 switch (MI->getOpcode()) { 2142 assert(MI->getNumOperands() >= 6 && 2145 const MachineOperand &MaskOp = MI->getOperand(MaskIdx); 2146 if (auto *C = getConstantFromPool(*MI, MaskOp)) { 2147 unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]); 2151 OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask)); 2182 switch (MI->getOpcode()) { 2214 assert(MI->getNumOperands() >= 6 && 2217 const MachineOperand &MaskOp = MI->getOperand(MaskIdx); 2218 if (auto *C = getConstantFromPool(*MI, MaskOp)) { 2219 unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]); 2223 OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask)); 2234 assert(MI->getNumOperands() >= 8 && 2237 const MachineOperand &CtrlOp = MI->getOperand(MI->getNumOperands() - 1); 2237 const MachineOperand &CtrlOp = MI->getOperand(MI->getNumOperands() - 1); 2242 switch (MI->getOpcode()) { 2248 const MachineOperand &MaskOp = MI->getOperand(6); 2249 if (auto *C = getConstantFromPool(*MI, MaskOp)) { 2250 unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]); 2254 OutStreamer->AddComment(getShuffleComment(MI, 1, 2, Mask)); 2262 assert(MI->getNumOperands() >= 7 && 2265 const MachineOperand &MaskOp = MI->getOperand(6); 2266 if (auto *C = getConstantFromPool(*MI, MaskOp)) { 2267 unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]); 2271 OutStreamer->AddComment(getShuffleComment(MI, 1, 2, Mask)); 2279 if (MI->getNumOperands() <= 4) 2281 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) { 2281 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) { 2284 const MachineOperand &DstOp = MI->getOperand(0); 2341 if (MI->getNumOperands() <= 4) 2343 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) { 2343 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) { 2346 switch (MI->getOpcode()) { 2365 const MachineOperand &DstOp = MI->getOperand(0); 2434 if (MI->getNumOperands() <= 4) 2436 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) { 2436 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) { 2438 switch (MI->getOpcode()) { 2475 const MachineOperand &DstOp = MI->getOperand(0); 2489 MCInstLowering.Lower(MI, TmpInst); 2495 if (MI->isCall()) {