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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenGlobalISel.inc 781 if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
lib/Target/X86/X86InstructionSelector.cpp 198 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI);
233 const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI);
234 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
237 const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI);
238 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
273 DstSize <= RBI.getSizeInBits(SrcReg, MRI, TRI))) &&
288 I.getOperand(1).substPhysReg(SrcReg, TRI);
508 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
546 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
583 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
629 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
641 if (RBI.getRegBank(DefReg, MRI, TRI)->getID() != X86::GPRRegBankID)
676 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
717 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
718 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
755 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubIdx);
806 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
807 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
875 constrainSelectedInstRegOperands(AndInst, TII, TRI, RBI);
892 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
893 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
980 constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI);
981 constrainSelectedInstRegOperands(SetInst, TII, TRI, RBI);
1030 *getRegClass(LLT::scalar(8), *RBI.getRegBank(ResultReg, MRI, TRI)), MRI);
1047 constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI);
1048 constrainSelectedInstRegOperands(Set1, TII, TRI, RBI);
1049 constrainSelectedInstRegOperands(Set2, TII, TRI, RBI);
1050 constrainSelectedInstRegOperands(Set3, TII, TRI, RBI);
1072 constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI);
1073 constrainSelectedInstRegOperands(Set, TII, TRI, RBI);
1129 if (!constrainSelectedInstRegOperands(AddInst, TII, TRI, RBI) ||
1191 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1218 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubIdx);
1325 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1367 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);
1417 constrainSelectedInstRegOperands(TestInst, TII, TRI, RBI);
1436 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);
1484 constrainSelectedInstRegOperands(*LoadInst, TII, TRI, RBI);
1534 const RegisterBank *RegRB = RBI.getRegBank(DstReg, MRI, TRI);