reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
781 if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
lib/Target/X86/X86InstructionSelector.cpp254 TII.get(TargetOpcode::SUBREG_TO_REG)) 298 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) 303 I.setDesc(TII.get(X86::COPY)); 535 I.setDesc(TII.get(NewOpc)); 546 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); 571 I.setDesc(TII.get(NewOpc)); 583 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); 623 I.setDesc(TII.get(NewOpc)); 629 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); 675 I.setDesc(TII.get(NewOpc)); 676 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); 696 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) 700 I.setDesc(TII.get(X86::COPY)); 721 LLVM_DEBUG(dbgs() << TII.getName(I.getOpcode()) 759 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) 766 I.setDesc(TII.get(X86::COPY)); 813 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) 829 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(ZextEntryIt->MovOp)) 835 TII.get(TargetOpcode::SUBREG_TO_REG)) 864 TII.get(TargetOpcode::SUBREG_TO_REG), DefReg) 871 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AndOpc), DstReg) 875 constrainSelectedInstRegOperands(AndInst, TII, TRI, RBI); 915 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) 921 I.setDesc(TII.get(X86::COPY)); 926 TII.get(TargetOpcode::SUBREG_TO_REG)) 973 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp)) 978 TII.get(X86::SETCCr), I.getOperand(0).getReg()).addImm(CC); 980 constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI); 981 constrainSelectedInstRegOperands(SetInst, TII, TRI, RBI); 1033 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp)) 1040 TII.get(X86::SETCCr), FlagReg1).addImm(SETFOpc[0]); 1042 TII.get(X86::SETCCr), FlagReg2).addImm(SETFOpc[1]); 1044 TII.get(SETFOpc[2]), ResultReg) 1047 constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI); 1048 constrainSelectedInstRegOperands(Set1, TII, TRI, RBI); 1049 constrainSelectedInstRegOperands(Set2, TII, TRI, RBI); 1050 constrainSelectedInstRegOperands(Set3, TII, TRI, RBI); 1066 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp)) 1071 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SETCCr), ResultReg).addImm(CC); 1072 constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI); 1073 constrainSelectedInstRegOperands(Set, TII, TRI, RBI); 1105 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), X86::EFLAGS) 1122 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode), DstReg) 1126 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), CarryOutReg) 1129 if (!constrainSelectedInstRegOperands(AddInst, TII, TRI, RBI) || 1172 I.setDesc(TII.get(X86::VEXTRACTF32x4Z256rr)); 1174 I.setDesc(TII.get(X86::VEXTRACTF128rr)); 1179 I.setDesc(TII.get(X86::VEXTRACTF32x4Zrr)); 1181 I.setDesc(TII.get(X86::VEXTRACTF64x4Zrr)); 1191 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); 1226 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), DstReg) 1263 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY)) 1305 I.setDesc(TII.get(X86::VINSERTF32x4Z256rr)); 1307 I.setDesc(TII.get(X86::VINSERTF128rr)); 1312 I.setDesc(TII.get(X86::VINSERTF32x4Zrr)); 1314 I.setDesc(TII.get(X86::VINSERTF64x4Zrr)); 1325 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); 1341 TII.get(TargetOpcode::G_EXTRACT), I.getOperand(Idx).getReg()) 1380 TII.get(TargetOpcode::G_INSERT), Tmp) 1392 TII.get(TargetOpcode::COPY), DstReg) 1411 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::TEST8ri)) 1414 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::JCC_1)) 1417 constrainSelectedInstRegOperands(TestInst, TII, TRI, RBI); 1453 BuildMI(*I.getParent(), I, DbgLoc, TII.get(X86::MOV64ri), AddrReg) 1461 addDirectMem(BuildMI(*I.getParent(), I, DbgLoc, TII.get(Opc), DstReg), 1479 BuildMI(*I.getParent(), I, DbgLoc, TII.get(Opc), DstReg), CPI, PICBase, 1484 constrainSelectedInstRegOperands(*LoadInst, TII, TRI, RBI); 1502 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) 1509 I.setDesc(TII.get(X86::IMPLICIT_DEF)); 1511 I.setDesc(TII.get(X86::PHI)); 1637 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) 1643 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpCopy), 1650 TII.get(OpEntry.OpSignExtend)); 1653 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::MOV32r0), 1660 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy), 1664 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy), 1669 TII.get(TargetOpcode::SUBREG_TO_REG), TypeEntry.HighInReg) 1677 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpDivRem)) 1692 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy), SourceSuperReg) 1696 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SHR16ri), 1703 TII.get(TargetOpcode::SUBREG_TO_REG)) 1709 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::COPY), 1726 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::TRAP));