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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenGlobalISel.inc 781 if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
lib/Target/X86/X86InstructionSelector.cpp 198 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI);
233 const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI);
234 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
237 const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI);
238 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
273 DstSize <= RBI.getSizeInBits(SrcReg, MRI, TRI))) &&
297 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
508 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
546 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
583 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
629 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
641 if (RBI.getRegBank(DefReg, MRI, TRI)->getID() != X86::GPRRegBankID)
676 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
694 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
695 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
717 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
718 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
757 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
758 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
806 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
807 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
811 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
812 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
875 constrainSelectedInstRegOperands(AndInst, TII, TRI, RBI);
892 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
893 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
913 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
914 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
980 constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI);
981 constrainSelectedInstRegOperands(SetInst, TII, TRI, RBI);
1028 RBI.constrainGenericRegister(
1030 *getRegClass(LLT::scalar(8), *RBI.getRegBank(ResultReg, MRI, TRI)), MRI);
1047 constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI);
1048 constrainSelectedInstRegOperands(Set1, TII, TRI, RBI);
1049 constrainSelectedInstRegOperands(Set2, TII, TRI, RBI);
1050 constrainSelectedInstRegOperands(Set3, TII, TRI, RBI);
1072 constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI);
1073 constrainSelectedInstRegOperands(Set, TII, TRI, RBI);
1108 if (!RBI.constrainGenericRegister(CarryInReg, X86::GR32RegClass, MRI))
1129 if (!constrainSelectedInstRegOperands(AddInst, TII, TRI, RBI) ||
1130 !RBI.constrainGenericRegister(CarryOutReg, X86::GR32RegClass, MRI))
1191 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1220 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
1221 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
1257 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
1258 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
1325 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
1367 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);
1417 constrainSelectedInstRegOperands(TestInst, TII, TRI, RBI);
1436 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);
1484 constrainSelectedInstRegOperands(*LoadInst, TII, TRI, RBI);
1501 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
1534 const RegisterBank *RegRB = RBI.getRegBank(DstReg, MRI, TRI);
1634 if (!RBI.constrainGenericRegister(Op1Reg, *RegRC, MRI) ||
1635 !RBI.constrainGenericRegister(Op2Reg, *RegRC, MRI) ||
1636 !RBI.constrainGenericRegister(DstReg, *RegRC, MRI)) {