reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
1520 assert((I.getOpcode() == TargetOpcode::G_SDIV || 1521 I.getOpcode() == TargetOpcode::G_SREM || 1522 I.getOpcode() == TargetOpcode::G_UDIV || 1523 I.getOpcode() == TargetOpcode::G_UREM) && 1526 const Register DstReg = I.getOperand(0).getReg(); 1527 const Register Op1Reg = I.getOperand(1).getReg(); 1528 const Register Op2Reg = I.getOperand(2).getReg(); 1613 switch (I.getOpcode()) { 1637 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) 1643 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpCopy), 1643 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpCopy), 1643 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpCopy), 1649 BuildMI(*I.getParent(), I, I.getDebugLoc(), 1649 BuildMI(*I.getParent(), I, I.getDebugLoc(), 1649 BuildMI(*I.getParent(), I, I.getDebugLoc(), 1653 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::MOV32r0), 1653 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::MOV32r0), 1653 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::MOV32r0), 1660 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy), 1660 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy), 1660 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy), 1664 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy), 1664 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy), 1664 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy), 1668 BuildMI(*I.getParent(), I, I.getDebugLoc(), 1668 BuildMI(*I.getParent(), I, I.getDebugLoc(), 1668 BuildMI(*I.getParent(), I, I.getDebugLoc(), 1677 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpDivRem)) 1677 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpDivRem)) 1677 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpDivRem)) 1687 if ((I.getOpcode() == Instruction::SRem || 1688 I.getOpcode() == Instruction::URem) && 1692 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy), SourceSuperReg) 1692 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy), SourceSuperReg) 1692 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy), SourceSuperReg) 1696 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SHR16ri), 1696 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SHR16ri), 1696 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SHR16ri), 1702 BuildMI(*I.getParent(), I, I.getDebugLoc(), 1702 BuildMI(*I.getParent(), I, I.getDebugLoc(), 1702 BuildMI(*I.getParent(), I, I.getDebugLoc(), 1709 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::COPY), 1709 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::COPY), 1709 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::COPY), 1713 I.eraseFromParent();