reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
990 assert((I.getOpcode() == TargetOpcode::G_FCMP) && "unexpected instruction"); 992 Register LhsReg = I.getOperand(2).getReg(); 993 Register RhsReg = I.getOperand(3).getReg(); 995 (CmpInst::Predicate)I.getOperand(1).getPredicate(); 1027 Register ResultReg = I.getOperand(0).getReg(); 1033 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp)) 1033 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp)) 1033 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp)) 1039 MachineInstr &Set1 = *BuildMI(*I.getParent(), I, I.getDebugLoc(), 1039 MachineInstr &Set1 = *BuildMI(*I.getParent(), I, I.getDebugLoc(), 1039 MachineInstr &Set1 = *BuildMI(*I.getParent(), I, I.getDebugLoc(), 1041 MachineInstr &Set2 = *BuildMI(*I.getParent(), I, I.getDebugLoc(), 1041 MachineInstr &Set2 = *BuildMI(*I.getParent(), I, I.getDebugLoc(), 1041 MachineInstr &Set2 = *BuildMI(*I.getParent(), I, I.getDebugLoc(), 1043 MachineInstr &Set3 = *BuildMI(*I.getParent(), I, I.getDebugLoc(), 1043 MachineInstr &Set3 = *BuildMI(*I.getParent(), I, I.getDebugLoc(), 1043 MachineInstr &Set3 = *BuildMI(*I.getParent(), I, I.getDebugLoc(), 1052 I.eraseFromParent(); 1066 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp)) 1066 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp)) 1066 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp)) 1071 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SETCCr), ResultReg).addImm(CC); 1071 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SETCCr), ResultReg).addImm(CC); 1071 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SETCCr), ResultReg).addImm(CC); 1074 I.eraseFromParent();