reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/Target/X86/X86ISelLowering.cpp
36827       return DAG.getVectorShuffle(VT, DL, LHS, RHS, Mask);
36835   if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
36836       VT != MVT::f80 && VT != MVT::f128 &&
36836       VT != MVT::f80 && VT != MVT::f128 &&
36837       (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
36837       (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
36839        (Subtarget.hasSSE1() && VT.getScalarType() == MVT::f32))) {
36990       Cond.getOpcode() == ISD::SETCC && (VT == MVT::f32 || VT == MVT::f64)) {
36990       Cond.getOpcode() == ISD::SETCC && (VT == MVT::f32 || VT == MVT::f64)) {
36999       return DAG.getNode(ISD::SELECT, DL, VT, AndNode, RHS, LHS);
37012       (VT.getVectorElementType() == MVT::i8 ||
37013        VT.getVectorElementType() == MVT::i16)) {
37014     Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Cond);
37015     return DAG.getNode(N->getOpcode(), DL, VT, Cond, LHS, RHS);
37043                             VT.getSizeInBits());
37045                             VT.getSizeInBits());
37050       return extractSubVector(Res, 0, DAG, DL, VT.getSizeInBits());
37084       return DAG.getSelect(DL, VT, Cond, LHS, RHS);
37092       Subtarget.hasSSE2() && VT.getVectorNumElements() >= 2 &&
37093       isPowerOf2_32(VT.getVectorNumElements()) &&
37094       (VT.getVectorElementType() == MVT::i8 ||
37095        VT.getVectorElementType() == MVT::i16)) {
37118         return DAG.getNode(ISD::USUBSAT, DL, VT, OpLHS, OpRHS);
37133             OpRHS = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
37133             OpRHS = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
37135             return DAG.getNode(ISD::USUBSAT, DL, VT, OpLHS, OpRHS);
37149               OpRHS = DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT);
37150               return DAG.getNode(ISD::USUBSAT, DL, VT, OpLHS, OpRHS);
37161       Subtarget.hasSSE2() && VT.getVectorNumElements() >= 2 &&
37162       isPowerOf2_32(VT.getVectorNumElements()) &&
37163       (VT.getVectorElementType() == MVT::i8 ||
37164        VT.getVectorElementType() == MVT::i16)) {
37194         return DAG.getNode(ISD::UADDSAT, DL, VT, OpLHS, OpRHS);
37206           return DAG.getNode(ISD::UADDSAT, DL, VT, OpLHS, OpRHS);
37212   if (!TLI.isTypeLegal(VT))
37227       return DAG.getNode(N->getOpcode(), DL, VT,
37231   if (VT == MVT::x86mmx) {
37235     return DAG.getBitcast(VT, newSelect);