|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
lib/Target/X86/X86ISelLowering.cpp26245 assert(VT.isVector() && "Custom lowering only for vector rotates!");
26251 unsigned EltSizeInBits = VT.getScalarSizeInBits();
26252 int NumElts = VT.getVectorNumElements();
26275 return DAG.getNode(Op, DL, VT, R,
26289 if (VT.is256BitVector())
26291 assert(VT.is128BitVector() && "Only rotate 128-bit vectors!");
26296 return DAG.getNode(X86ISD::VROTLI, DL, VT, R,
26305 if (VT.is256BitVector() && !Subtarget.hasAVX2())
26308 assert((VT == MVT::v4i32 || VT == MVT::v8i16 || VT == MVT::v16i8 ||
26308 assert((VT == MVT::v4i32 || VT == MVT::v8i16 || VT == MVT::v16i8 ||
26308 assert((VT == MVT::v4i32 || VT == MVT::v8i16 || VT == MVT::v16i8 ||
26309 ((VT == MVT::v8i32 || VT == MVT::v16i16 || VT == MVT::v32i8) &&
26309 ((VT == MVT::v8i32 || VT == MVT::v16i16 || VT == MVT::v32i8) &&
26309 ((VT == MVT::v8i32 || VT == MVT::v16i16 || VT == MVT::v32i8) &&
26332 V0 = DAG.getBitcast(VT, V0);
26333 V1 = DAG.getBitcast(VT, V1);
26334 Sel = DAG.getBitcast(VT, Sel);
26335 return DAG.getBitcast(SelVT, DAG.getSelect(DL, VT, Sel, V0, V1));
26350 Amt = DAG.getBitcast(VT, Amt);
26355 ISD::OR, DL, VT,
26356 DAG.getNode(ISD::SHL, DL, VT, R, DAG.getConstant(4, DL, VT)),
26356 DAG.getNode(ISD::SHL, DL, VT, R, DAG.getConstant(4, DL, VT)),
26357 DAG.getNode(ISD::SRL, DL, VT, R, DAG.getConstant(4, DL, VT)));
26357 DAG.getNode(ISD::SRL, DL, VT, R, DAG.getConstant(4, DL, VT)));
26358 R = SignBitSelect(VT, Amt, M, R);
26361 Amt = DAG.getNode(ISD::ADD, DL, VT, Amt, Amt);
26365 ISD::OR, DL, VT,
26366 DAG.getNode(ISD::SHL, DL, VT, R, DAG.getConstant(2, DL, VT)),
26366 DAG.getNode(ISD::SHL, DL, VT, R, DAG.getConstant(2, DL, VT)),
26367 DAG.getNode(ISD::SRL, DL, VT, R, DAG.getConstant(6, DL, VT)));
26367 DAG.getNode(ISD::SRL, DL, VT, R, DAG.getConstant(6, DL, VT)));
26368 R = SignBitSelect(VT, Amt, M, R);
26371 Amt = DAG.getNode(ISD::ADD, DL, VT, Amt, Amt);
26375 ISD::OR, DL, VT,
26376 DAG.getNode(ISD::SHL, DL, VT, R, DAG.getConstant(1, DL, VT)),
26376 DAG.getNode(ISD::SHL, DL, VT, R, DAG.getConstant(1, DL, VT)),
26377 DAG.getNode(ISD::SRL, DL, VT, R, DAG.getConstant(7, DL, VT)));
26377 DAG.getNode(ISD::SRL, DL, VT, R, DAG.getConstant(7, DL, VT)));
26378 return SignBitSelect(VT, Amt, M, R);
26382 Amt = DAG.getNode(ISD::AND, DL, VT, Amt,
26383 DAG.getConstant(EltSizeInBits - 1, DL, VT));
26386 bool LegalVarShifts = SupportedVectorVarShift(VT, Subtarget, ISD::SHL) &&
26387 SupportedVectorVarShift(VT, Subtarget, ISD::SRL);
26392 SDValue AmtR = DAG.getConstant(EltSizeInBits, DL, VT);
26393 AmtR = DAG.getNode(ISD::SUB, DL, VT, AmtR, Amt);
26394 SDValue SHL = DAG.getNode(ISD::SHL, DL, VT, R, Amt);
26395 SDValue SRL = DAG.getNode(ISD::SRL, DL, VT, R, AmtR);
26396 return DAG.getNode(ISD::OR, DL, VT, SHL, SRL);
26405 SDValue Lo = DAG.getNode(ISD::MUL, DL, VT, R, Scale);
26406 SDValue Hi = DAG.getNode(ISD::MULHU, DL, VT, R, Scale);
26407 return DAG.getNode(ISD::OR, DL, VT, Lo, Hi);
26413 assert(VT == MVT::v4i32 && "Only v4i32 vector rotate expected");
26415 SDValue R13 = DAG.getVectorShuffle(VT, DL, R, R, OddMask);
26416 SDValue Scale13 = DAG.getVectorShuffle(VT, DL, Scale, Scale, OddMask);
26424 Res02 = DAG.getBitcast(VT, Res02);
26425 Res13 = DAG.getBitcast(VT, Res13);
26427 return DAG.getNode(ISD::OR, DL, VT,
26428 DAG.getVectorShuffle(VT, DL, Res02, Res13, {0, 4, 2, 6}),
26429 DAG.getVectorShuffle(VT, DL, Res02, Res13, {1, 5, 3, 7}));