reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
25495 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type"); 25495 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type"); 25496 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2); 25501 assert((VT != MVT::v4i64 || Subtarget.hasInt256()) && 25503 return DAG.getNode(X86ISD::PCMPGT, dl, VT, DAG.getConstant(0, dl, VT), R); 25503 return DAG.getNode(X86ISD::PCMPGT, dl, VT, DAG.getConstant(0, dl, VT), R); 25512 if (VT == MVT::v2i64) 25514 if (VT == MVT::v4i64) 25522 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG); 25524 if (VT == MVT::v2i64) 25526 if (VT == MVT::v4i64) 25530 return DAG.getBitcast(VT, Ex); 25539 if (APIntShiftAmt.uge(VT.getScalarSizeInBits())) 25540 return DAG.getUNDEF(VT); 25544 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode())) 25545 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG); 25548 if (((!Subtarget.hasXOP() && VT == MVT::v2i64) || 25549 (Subtarget.hasInt256() && VT == MVT::v4i64)) && 25553 if (VT == MVT::v16i8 || (Subtarget.hasInt256() && VT == MVT::v32i8) || 25553 if (VT == MVT::v16i8 || (Subtarget.hasInt256() && VT == MVT::v32i8) || 25554 VT == MVT::v64i8) { 25555 unsigned NumElts = VT.getVectorNumElements(); 25560 return DAG.getNode(ISD::ADD, dl, VT, R, R); 25564 SDValue Zeros = DAG.getConstant(0, dl, VT); 25565 if (VT.is512BitVector()) { 25566 assert(VT == MVT::v64i8 && "Unexpected element type!"); 25568 return DAG.getNode(ISD::SIGN_EXTEND, dl, VT, CMP); 25570 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); 25574 if (VT == MVT::v16i8 && Subtarget.hasXOP()) 25581 SHL = DAG.getBitcast(VT, SHL); 25584 return DAG.getNode(ISD::AND, dl, VT, SHL, DAG.getConstant(Mask, dl, VT)); 25584 return DAG.getNode(ISD::AND, dl, VT, SHL, DAG.getConstant(Mask, dl, VT)); 25590 SRL = DAG.getBitcast(VT, SRL); 25592 return DAG.getNode(ISD::AND, dl, VT, SRL, 25593 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, VT)); 25597 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 25599 SDValue Mask = DAG.getConstant(128 >> ShiftAmt, dl, VT); 25600 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 25601 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);