reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
20643 if (Subtarget.hasAVX512() && VT.getVectorElementType() == MVT::i1) { 20644 assert(VT.getVectorNumElements() <= 16); 20651 VT = Op0.getSimpleValueType(); 20673 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1, 20675 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1, 20677 Cmp = DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1); 20680 Cmp = DAG.getNode(Opc, dl, VT, Op0, Op1, 20697 assert(VT.getVectorNumElements() == VTOp0.getVectorNumElements() && 20702 assert((Subtarget.hasAVX512() || (VT == VTOp0)) && 20706 if (VT.getVectorElementType() == MVT::i1) { 20715 if (VT.is128BitVector() && Subtarget.hasXOP()) { 20736 return DAG.getNode(Opc, dl, VT, Op0, Op1, 20748 VT.getScalarSizeInBits(), UndefElts, 20752 Op1 = DAG.getBitcast(VT, BC0.getOperand(1)); 20763 unsigned BitWidth = VT.getScalarSizeInBits(); 20767 Result = DAG.getNode(ISD::SHL, dl, VT, Result, 20768 DAG.getConstant(ShiftAmt, dl, VT)); 20769 Result = DAG.getNode(ISD::SRA, dl, VT, Result, 20770 DAG.getConstant(BitWidth - 1, dl, VT)); 20776 if (VT.is256BitVector() && !Subtarget.hasInt256()) 20803 TLI.isOperationLegal(ISD::UMIN, VT)) { 20830 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 20831 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result); 20835 Result = DAG.getNOT(dl, Result, VT); 20841 if (SDValue V = LowerVSETCCWithSUBUS(Op0, Op1, VT, Cond, dl, Subtarget, DAG)) 20859 if (VT == MVT::v2i64) { 20896 return DAG.getBitcast(VT, Result); 20919 return DAG.getBitcast(VT, Result); 20926 MVT EltVT = VT.getVectorElementType(); 20928 VT); 20929 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SM); 20930 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SM); 20933 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 20937 Result = DAG.getNOT(dl, Result, VT);