reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
35463 EVT SrcVT = N0.getValueType(); 35473 if (SDValue V = combineBitcastvxi1(DAG, VT, N0, dl, Subtarget)) 35479 VT.isScalarInteger() && N0.getOpcode() == ISD::SETCC && 35480 N0.getOperand(0).getValueType() == MVT::v4i32 && 35481 ISD::isBuildVectorAllZeros(N0.getOperand(1).getNode()) && 35482 cast<CondCodeSDNode>(N0.getOperand(2))->get() == ISD::SETLT) { 35483 SDValue N00 = N0.getOperand(0); 35498 N0 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, N0); 35498 N0 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, N0); 35499 N0 = DAG.getBitcast(MVT::v8i1, N0); 35499 N0 = DAG.getBitcast(MVT::v8i1, N0); 35500 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, N0, 35515 if (N0.getOpcode() == ISD::CONCAT_VECTORS) { 35516 SDValue LastOp = N0.getOperand(N0.getNumOperands() - 1); 35516 SDValue LastOp = N0.getOperand(N0.getNumOperands() - 1); 35520 SmallVector<SDValue, 4> Ops(N0->op_begin(), N0->op_end()); 35520 SmallVector<SDValue, 4> Ops(N0->op_begin(), N0->op_end()); 35522 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i1, Ops); 35523 N0 = DAG.getBitcast(MVT::i8, N0); 35523 N0 = DAG.getBitcast(MVT::i8, N0); 35524 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); 35530 Ops[0] = N0; 35531 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i1, Ops); 35532 N0 = DAG.getBitcast(MVT::i8, N0); 35532 N0 = DAG.getBitcast(MVT::i8, N0); 35533 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); 35543 !Subtarget.hasDQI() && N0.getOpcode() == ISD::EXTRACT_SUBVECTOR && 35544 N0.getOperand(0).getValueType() == MVT::v16i1 && 35545 isNullConstant(N0.getOperand(1))) 35547 DAG.getBitcast(MVT::i16, N0.getOperand(0))); 35551 if (N0.getOpcode() == X86ISD::VBROADCAST_LOAD && N0.hasOneUse() && 35551 if (N0.getOpcode() == X86ISD::VBROADCAST_LOAD && N0.hasOneUse() && 35553 auto *BCast = cast<MemIntrinsicSDNode>(N0); 35571 if (getTargetConstantBitsFromNode(N0, 64, UndefElts, EltBits)) { 35572 SDLoc DL(N0); 35584 if (N0.getOpcode() == ISD::BUILD_VECTOR && 35586 N0.getOperand(0).getValueType() == SrcVT.getScalarType()) { 35589 SDValue Op = N0.getOperand(i); 35594 SDValue N00 = N0.getOperand(0); 35605 if (N0.getOpcode() == ISD::BUILD_VECTOR && 35608 return createMMXBuildVector(cast<BuildVectorSDNode>(N0), DAG, Subtarget); 35611 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT || 35612 N0.getOpcode() == ISD::EXTRACT_SUBVECTOR) && 35613 isNullConstant(N0.getOperand(1))) { 35614 SDValue N00 = N0.getOperand(0); 35621 if (SrcVT == MVT::v2i32 && N0.getOpcode() == ISD::FP_TO_SINT) { 35622 SDLoc DL(N0); 35623 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4i32, N0, 35634 ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) { 35635 return combinevXi1ConstantToInteger(N0, DAG); 35640 isa<ConstantSDNode>(N0)) { 35641 auto *C = cast<ConstantSDNode>(N0); 35643 return DAG.getConstant(1, SDLoc(N0), VT); 35645 return DAG.getConstant(0, SDLoc(N0), VT); 35659 switch (N0.getOpcode()) { 35670 SDValue LogicOp0 = N0.getOperand(0); 35671 SDValue LogicOp1 = N0.getOperand(1); 35672 SDLoc DL0(N0); 35675 if (N0.hasOneUse() && LogicOp0.getOpcode() == ISD::BITCAST && 35682 if (N0.hasOneUse() && LogicOp1.getOpcode() == ISD::BITCAST &&