reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
36275 DAG.matchBinOpReduction(ExtElt, Opc, {ISD::ADD, ISD::FADD}, true); 36295 Rdx = DAG.getBitcast(MVT::i32, Rdx); 36296 Rdx = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, MVT::v4i32, 36297 DAG.getConstant(0, DL, MVT::v4i32), Rdx, 36298 DAG.getIntPtrConstant(0, DL)); 36299 Rdx = DAG.getBitcast(MVT::v16i8, Rdx); 36301 Rdx = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i8, Rdx, 36302 DAG.getConstant(0, DL, VecVT)); 36307 Rdx = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, Rdx, 36308 DAG.getUNDEF(MVT::v8i8)); 36310 Rdx = DAG.getNode(X86ISD::PSADBW, DL, MVT::v2i64, Rdx, 36311 DAG.getConstant(0, DL, MVT::v16i8)); 36312 Rdx = DAG.getBitcast(MVT::v16i8, Rdx); 36313 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Rdx, Index); 36326 SDValue Lo = extractSubVector(Rdx, 0, DAG, DL, HalfSize); 36327 SDValue Hi = extractSubVector(Rdx, HalfElts, DAG, DL, HalfSize); 36328 Rdx = DAG.getNode(ISD::ADD, DL, Lo.getValueType(), Lo, Hi); 36333 SDValue Hi = DAG.getVectorShuffle( 36336 Rdx = DAG.getNode(ISD::ADD, DL, MVT::v16i8, Rdx, Hi); 36337 Rdx = DAG.getNode(X86ISD::PSADBW, DL, MVT::v2i64, Rdx, 36338 getZeroVector(MVT::v16i8, Subtarget, DAG, DL)); 36339 Rdx = DAG.getBitcast(MVT::v16i8, Rdx); 36340 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Rdx, Index); 36344 bool OptForSize = DAG.getMachineFunction().getFunction().hasOptSize(); 36357 SDValue Hi = extract128BitVector(Rdx, NumElts / 2, DAG, DL); 36358 SDValue Lo = extract128BitVector(Rdx, 0, DAG, DL); 36359 Rdx = DAG.getNode(HorizOpcode, DL, Lo.getValueType(), Hi, Lo); 36369 Rdx = DAG.getNode(HorizOpcode, DL, VecVT, Rdx, Rdx); 36371 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Rdx, Index);