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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
lib/Target/X86/X86ISelLowering.cpp32301 SDValue V2 = (UnaryShuffle ? DAG.getUNDEF(V1.getValueType())
32317 return DAG.getBitcast(RootVT, V1);
32347 return DAG.getBitcast(RootVT, DAG.getNode(X86ISD::SUBV_BROADCAST, DL,
32347 return DAG.getBitcast(RootVT, DAG.getNode(X86ISD::SUBV_BROADCAST, DL,
32370 Res = DAG.getBitcast(ShuffleVT, V1);
32371 Res = DAG.getNode(X86ISD::VPERM2X128, DL, ShuffleVT, Res,
32372 DAG.getUNDEF(ShuffleVT),
32373 DAG.getTargetConstant(PermMask, DL, MVT::i8));
32374 return DAG.getBitcast(RootVT, Res);
32398 if (!DAG.getTargetLoweringInfo().isTypeLegal(MaskVT))
32431 return DAG.getBitcast(RootVT, V1);
32447 Res = DAG.getNode(X86ISD::VBROADCAST, DL, MaskVT, Res);
32448 return DAG.getBitcast(RootVT, Res);
32453 Res = DAG.getBitcast(MaskVT, V1);
32454 Res = DAG.getNode(X86ISD::VBROADCAST, DL, MaskVT, Res);
32455 return DAG.getBitcast(RootVT, Res);
32462 DL, DAG, Subtarget, Shuffle, ShuffleSrcVT,
32467 Res = DAG.getBitcast(ShuffleSrcVT, NewV1);
32468 Res = DAG.getNode(Shuffle, DL, ShuffleVT, Res);
32469 return DAG.getBitcast(RootVT, Res);
32478 Res = DAG.getBitcast(ShuffleVT, V1);
32479 Res = DAG.getNode(Shuffle, DL, ShuffleVT, Res,
32480 DAG.getTargetConstant(PermuteImm, DL, MVT::i8));
32481 return DAG.getBitcast(RootVT, Res);
32488 NewV2, DL, DAG, Subtarget, Shuffle, ShuffleSrcVT,
32493 NewV1 = DAG.getBitcast(ShuffleSrcVT, NewV1);
32494 NewV2 = DAG.getBitcast(ShuffleSrcVT, NewV2);
32495 Res = DAG.getNode(Shuffle, DL, ShuffleVT, NewV1, NewV2);
32496 return DAG.getBitcast(RootVT, Res);
32503 NewV2, DL, DAG, Subtarget, Shuffle, ShuffleVT, PermuteImm) &&
32507 NewV1 = DAG.getBitcast(ShuffleVT, NewV1);
32508 NewV2 = DAG.getBitcast(ShuffleVT, NewV2);
32509 Res = DAG.getNode(Shuffle, DL, ShuffleVT, NewV1, NewV2,
32510 DAG.getTargetConstant(PermuteImm, DL, MVT::i8));
32511 return DAG.getBitcast(RootVT, Res);
32525 V1 = DAG.getBitcast(IntMaskVT, V1);
32526 Res = DAG.getNode(X86ISD::EXTRQI, DL, IntMaskVT, V1,
32527 DAG.getTargetConstant(BitLen, DL, MVT::i8),
32528 DAG.getTargetConstant(BitIdx, DL, MVT::i8));
32529 return DAG.getBitcast(RootVT, Res);
32535 V1 = DAG.getBitcast(IntMaskVT, V1);
32536 V2 = DAG.getBitcast(IntMaskVT, V2);
32537 Res = DAG.getNode(X86ISD::INSERTQI, DL, IntMaskVT, V1, V2,
32538 DAG.getTargetConstant(BitLen, DL, MVT::i8),
32539 DAG.getTargetConstant(BitIdx, DL, MVT::i8));
32540 return DAG.getBitcast(RootVT, Res);
32568 SDValue VPermMask = getConstVector(Mask, IntMaskVT, DAG, DL, true);
32569 Res = DAG.getBitcast(MaskVT, V1);
32570 Res = DAG.getNode(X86ISD::VPERMV, DL, MaskVT, VPermMask, Res);
32571 return DAG.getBitcast(RootVT, Res);
32592 SDValue VPermMask = getConstVector(Mask, IntMaskVT, DAG, DL, true);
32593 Res = DAG.getBitcast(MaskVT, V1);
32594 SDValue Zero = getZeroVector(MaskVT, Subtarget, DAG, DL);
32595 Res = DAG.getNode(X86ISD::VPERMV3, DL, MaskVT, Res, VPermMask, Zero);
32596 return DAG.getBitcast(RootVT, Res);
32603 DAG, Subtarget))
32618 SDValue VPermMask = getConstVector(Mask, IntMaskVT, DAG, DL, true);
32619 V1 = DAG.getBitcast(MaskVT, V1);
32620 V2 = DAG.getBitcast(MaskVT, V2);
32621 Res = DAG.getNode(X86ISD::VPERMV3, DL, MaskVT, V1, VPermMask, V2);
32622 return DAG.getBitcast(RootVT, Res);
32631 DAG.getTargetLoweringInfo().isTypeLegal(MaskVT)) {
32646 SDValue BitMask = getConstVector(EltBits, UndefElts, MaskVT, DAG, DL);
32647 Res = DAG.getBitcast(MaskVT, V1);
32650 Res = DAG.getNode(AndOpcode, DL, MaskVT, Res, BitMask);
32651 return DAG.getBitcast(RootVT, Res);
32663 M < 0 ? DAG.getUNDEF(MVT::i32) : DAG.getConstant(M % 4, DL, MVT::i32);
32663 M < 0 ? DAG.getUNDEF(MVT::i32) : DAG.getConstant(M % 4, DL, MVT::i32);
32666 SDValue VPermMask = DAG.getBuildVector(IntMaskVT, DL, VPermIdx);
32667 Res = DAG.getBitcast(MaskVT, V1);
32668 Res = DAG.getNode(X86ISD::VPERMILPV, DL, MaskVT, Res, VPermMask);
32669 return DAG.getBitcast(RootVT, Res);
32699 V1 = DAG.getBitcast(MaskVT, V1);
32700 V2 = DAG.getBitcast(MaskVT, V2);
32701 SDValue VPerm2MaskOp = getConstVector(VPerm2Idx, IntMaskVT, DAG, DL, true);
32702 Res = DAG.getNode(X86ISD::VPERMIL2, DL, MaskVT, V1, V2, VPerm2MaskOp,
32703 DAG.getTargetConstant(M2ZImm, DL, MVT::i8));
32704 return DAG.getBitcast(RootVT, Res);
32722 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
32726 PSHUFBMask.push_back(DAG.getConstant(255, DL, MVT::i8));
32731 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
32734 Res = DAG.getBitcast(ByteVT, V1);
32735 SDValue PSHUFBMaskOp = DAG.getBuildVector(ByteVT, DL, PSHUFBMask);
32736 Res = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Res, PSHUFBMaskOp);
32737 return DAG.getBitcast(RootVT, Res);
32753 VPPERMMask.push_back(DAG.getUNDEF(MVT::i8));
32757 VPPERMMask.push_back(DAG.getConstant(128, DL, MVT::i8));
32761 VPPERMMask.push_back(DAG.getConstant(M, DL, MVT::i8));
32764 V1 = DAG.getBitcast(ByteVT, V1);
32765 V2 = DAG.getBitcast(ByteVT, V2);
32766 SDValue VPPERMMaskOp = DAG.getBuildVector(ByteVT, DL, VPPERMMask);
32767 Res = DAG.getNode(X86ISD::VPPERM, DL, ByteVT, V1, V2, VPPERMMaskOp);
32768 return DAG.getBitcast(RootVT, Res);
32775 DAG, Subtarget))
32793 SDValue VPermMask = getConstVector(Mask, IntMaskVT, DAG, DL, true);
32794 V1 = DAG.getBitcast(MaskVT, V1);
32795 V2 = DAG.getBitcast(MaskVT, V2);
32796 Res = DAG.getNode(X86ISD::VPERMV3, DL, MaskVT, V1, VPermMask, V2);
32797 return DAG.getBitcast(RootVT, Res);