|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
lib/Target/X86/X86ISelLowering.cpp25497 SDValue Ex = DAG.getBitcast(ExVT, R);
25503 return DAG.getNode(X86ISD::PCMPGT, dl, VT, DAG.getConstant(0, dl, VT), R);
25503 return DAG.getNode(X86ISD::PCMPGT, dl, VT, DAG.getConstant(0, dl, VT), R);
25509 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
25511 ShiftAmt - 32, DAG);
25513 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
25515 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
25520 ShiftAmt, DAG);
25522 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
25523 Lower = DAG.getBitcast(ExVT, Lower);
25525 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
25527 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
25530 return DAG.getBitcast(VT, Ex);
25540 return DAG.getUNDEF(VT);
25545 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
25560 return DAG.getNode(ISD::ADD, dl, VT, R, R);
25564 SDValue Zeros = DAG.getConstant(0, dl, VT);
25567 SDValue CMP = DAG.getSetCC(dl, MVT::v64i1, Zeros, R, ISD::SETGT);
25568 return DAG.getNode(ISD::SIGN_EXTEND, dl, VT, CMP);
25570 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
25580 ShiftAmt, DAG);
25581 SHL = DAG.getBitcast(VT, SHL);
25584 return DAG.getNode(ISD::AND, dl, VT, SHL, DAG.getConstant(Mask, dl, VT));
25584 return DAG.getNode(ISD::AND, dl, VT, SHL, DAG.getConstant(Mask, dl, VT));
25589 ShiftAmt, DAG);
25590 SRL = DAG.getBitcast(VT, SRL);
25592 return DAG.getNode(ISD::AND, dl, VT, SRL,
25593 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, VT));
25597 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
25599 SDValue Mask = DAG.getConstant(128 >> ShiftAmt, dl, VT);
25600 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
25601 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);