|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
lib/Target/X86/X86ISelLowering.cpp20673 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
20674 DAG.getTargetConstant(CC0, dl, MVT::i8));
20675 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
20676 DAG.getTargetConstant(CC1, dl, MVT::i8));
20677 Cmp = DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
20680 Cmp = DAG.getNode(Opc, dl, VT, Op0, Op1,
20681 DAG.getTargetConstant(SSECC, dl, MVT::i8));
20688 Cmp = DAG.getBitcast(Op.getSimpleValueType(), Cmp);
20711 return LowerIntVSETCC_AVX512(Op, DAG);
20736 return DAG.getNode(Opc, dl, VT, Op0, Op1,
20737 DAG.getTargetConstant(CmpMode, dl, MVT::i8));
20752 Op1 = DAG.getBitcast(VT, BC0.getOperand(1));
20767 Result = DAG.getNode(ISD::SHL, dl, VT, Result,
20768 DAG.getConstant(ShiftAmt, dl, VT));
20769 Result = DAG.getNode(ISD::SRA, dl, VT, Result,
20770 DAG.getConstant(BitWidth - 1, dl, VT));
20777 return Lower256IntVSETCC(Op, DAG);
20797 !(DAG.SignBitIsZero(Op0) && DAG.SignBitIsZero(Op1));
20797 !(DAG.SignBitIsZero(Op0) && DAG.SignBitIsZero(Op1));
20800 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20808 if (SDValue UGTOp1 = incDecVectorConstant(Op1, DAG, /*IsInc*/true)) {
20815 if (SDValue ULTOp1 = incDecVectorConstant(Op1, DAG, /*IsInc*/false)) {
20830 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
20831 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
20835 Result = DAG.getNOT(dl, Result, VT);
20841 if (SDValue V = LowerVSETCCWithSUBUS(Op0, Op1, VT, Cond, dl, Subtarget, DAG))
20868 SB = DAG.getConstant(0x8000000080000000ULL, dl, MVT::v2i64);
20870 SB = DAG.getConstant(0x0000000080000000ULL, dl, MVT::v2i64);
20872 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v2i64, Op0, SB);
20873 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v2i64, Op1, SB);
20876 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
20877 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
20880 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
20881 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
20886 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
20887 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
20888 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
20890 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
20891 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
20894 Result = DAG.getNOT(dl, Result, MVT::v4i32);
20896 return DAG.getBitcast(VT, Result);
20905 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
20906 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
20909 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
20913 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
20914 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
20917 Result = DAG.getNOT(dl, Result, MVT::v4i32);
20919 return DAG.getBitcast(VT, Result);
20927 SDValue SM = DAG.getConstant(APInt::getSignMask(EltVT.getSizeInBits()), dl,
20929 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SM);
20930 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SM);
20933 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
20937 Result = DAG.getNOT(dl, Result, VT);