|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
lib/Target/X86/X86ISelLowering.cpp14178 Zeroable, Subtarget, DAG))
14183 Subtarget, DAG))
14187 if (SDValue V = lowerShuffleWithPACK(DL, MVT::v16i8, Mask, V1, V2, DAG,
14193 Zeroable, Subtarget, DAG))
14199 Zeroable, DAG))
14208 Mask, Subtarget, DAG))
14211 if (SDValue V = lowerShuffleWithUNPCK(DL, MVT::v16i8, Mask, V1, V2, DAG))
14275 V1 = DAG.getBitcast(
14277 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
14277 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
14278 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
14288 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
14289 MVT::v16i8, EvenInUse ? V1 : DAG.getUNDEF(MVT::v16i8),
14290 OddInUse ? V1 : DAG.getUNDEF(MVT::v16i8));
14303 return DAG.getBitcast(
14305 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
14305 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
14306 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
14313 Zeroable, Subtarget, DAG))
14317 if (SDValue V = lowerShuffleWithUNPCK(DL, MVT::v16i8, Mask, V1, V2, DAG))
14322 DL, MVT::v16i8, V1, V2, Mask, Zeroable, Subtarget, DAG))
14343 DL, MVT::v16i8, V1, V2, Mask, Zeroable, DAG, V1InUse, V2InUse);
14351 Zeroable, Subtarget, DAG))
14363 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
14368 return lowerShuffleWithPERMV(DL, MVT::v16i8, Mask, V1, V2, DAG);
14373 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
14383 DL, MVT::v16i8, V1, V2, Mask, Zeroable, Subtarget, DAG))
14386 if (SDValue Blend = lowerShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
14405 SmallVector<SDValue, 16> ByteClearOps(16, DAG.getConstant(0, DL, MVT::i8));
14407 ByteClearOps[i] = DAG.getConstant(0xFF, DL, MVT::i8);
14408 SDValue ByteClearMask = DAG.getBuildVector(MVT::v16i8, DL, ByteClearOps);
14409 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
14411 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
14414 V1 = DAG.getBitcast(MVT::v8i16, V1);
14415 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
14416 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
14418 Result = DAG.getBitcast(MVT::v8i16, Result);
14419 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
14428 Subtarget, DAG);
14448 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
14449 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
14450 DAG.getConstant(0x00FF, DL, MVT::v8i16));
14453 VHiHalf = DAG.getUNDEF(MVT::v8i16);
14465 SDValue Zero = getZeroVector(MVT::v16i8, Subtarget, DAG, DL);
14467 VLoHalf = DAG.getBitcast(
14468 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
14469 VHiHalf = DAG.getBitcast(
14470 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
14473 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
14474 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
14476 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);