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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
lib/Target/X86/X86ISelLowering.cpp25768 bool ConstantAmt = ISD::isBuildVectorOfConstantSDNodes(Amt.getNode());
25792 Amt = DAG.getNode(ISD::SUB, dl, VT, Zero, Amt);
25792 Amt = DAG.getNode(ISD::SUB, dl, VT, Zero, Amt);
25795 return DAG.getNode(X86ISD::VPSHL, dl, VT, R, Amt);
25797 return DAG.getNode(X86ISD::VPSHA, dl, VT, R, Amt);
25804 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
25804 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
25805 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
25805 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
25817 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
25818 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
25840 SDValue A = Amt->getOperand(i);
25880 if (SDValue Scale = convertShiftLeftToScale(Amt, dl, Subtarget, DAG))
25888 SDValue RAmt = DAG.getNode(ISD::SUB, dl, VT, EltBits, Amt);
25891 SDValue ZAmt = DAG.getSetCC(dl, VT, Amt, Zero, ISD::SETEQ);
25905 DAG.isKnownNeverZero(Amt))) {
25907 SDValue RAmt = DAG.getNode(ISD::SUB, dl, VT, EltBits, Amt);
25910 DAG.getSetCC(dl, VT, Amt, DAG.getConstant(0, dl, VT), ISD::SETEQ);
25912 DAG.getSetCC(dl, VT, Amt, DAG.getConstant(1, dl, VT), ISD::SETEQ);
25929 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
25930 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
25931 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
25932 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
25940 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
25941 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
25942 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
25943 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
25945 SDValue Amt01 = DAG.getBitcast(MVT::v8i16, Amt);
25992 Amt = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Amt);
25992 Amt = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Amt);
25994 DAG.getNode(Opc, dl, ExtVT, R, Amt));
26009 Amt = DAG.getZExtOrTrunc(Amt, dl, ExVT);
26009 Amt = DAG.getZExtOrTrunc(Amt, dl, ExVT);
26010 Amt = DAG.getNode(ISD::SUB, dl, ExVT, DAG.getConstant(8, dl, ExVT), Amt);
26010 Amt = DAG.getNode(ISD::SUB, dl, ExVT, DAG.getConstant(8, dl, ExVT), Amt);
26011 Amt = DAG.getNode(ISD::SHL, dl, ExVT, DAG.getConstant(1, dl, ExVT), Amt);
26011 Amt = DAG.getNode(ISD::SHL, dl, ExVT, DAG.getConstant(1, dl, ExVT), Amt);
26012 assert(ISD::isBuildVectorOfConstantSDNodes(Amt.getNode()) &&
26018 R = DAG.getNode(ISD::MUL, dl, ExVT, R, Amt);
26026 LoAmt.push_back(Amt.getOperand(i + j));
26027 HiAmt.push_back(Amt.getOperand(i + j + 8));
26082 Amt = DAG.getBitcast(ExtVT, Amt);
26082 Amt = DAG.getBitcast(ExtVT, Amt);
26083 Amt = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ExtVT, Amt, 5, DAG);
26083 Amt = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ExtVT, Amt, 5, DAG);
26084 Amt = DAG.getBitcast(VT, Amt);
26084 Amt = DAG.getBitcast(VT, Amt);
26089 R = SignBitSelect(VT, Amt, M, R);
26092 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
26092 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
26092 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
26096 R = SignBitSelect(VT, Amt, M, R);
26099 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
26099 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
26099 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
26103 R = SignBitSelect(VT, Amt, M, R);
26111 SDValue ALo = getUnpackl(DAG, dl, VT, DAG.getUNDEF(VT), Amt);
26112 SDValue AHi = getUnpackh(DAG, dl, VT, DAG.getUNDEF(VT), Amt);
26157 SDValue ALo = getUnpackl(DAG, dl, VT, Amt, Z);
26158 SDValue AHi = getUnpackh(DAG, dl, VT, Amt, Z);
26176 !ISD::isBuildVectorOfConstantSDNodes(Amt.getNode());
26200 Amt = DAG.getNode(
26202 getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Amt, 4, DAG),
26203 getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Amt, 12, DAG));
26205 Amt = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Amt, 12, DAG);
26205 Amt = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Amt, 12, DAG);
26210 R = SignBitSelect(Amt, M, R);
26213 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
26213 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
26213 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
26217 R = SignBitSelect(Amt, M, R);
26220 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
26220 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
26220 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
26224 R = SignBitSelect(Amt, M, R);
26227 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
26227 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
26227 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
26231 R = SignBitSelect(Amt, M, R);