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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
lib/Target/X86/X86FrameLowering.cpp 275 BuildMI(MBB, MBBI, DL, TII.get(MovRIOpc), Reg)
278 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AddSubRROpc), StackPtr)
292 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r))
301 BuildMI(MBB, MBBI, DL, TII.get(MovRIOpc), Rax)
304 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(X86::ADD64rr), Rax)
310 BuildMI(MBB, MBBI, DL, TII.get(X86::XCHG64rm), Rax).addReg(Rax),
313 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), StackPtr),
331 BuildMI(MBB, MBBI, DL, TII.get(Opc))
378 TII.get(getLEArOpcode(Uses64BitFramePtr)),
386 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
456 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
789 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::R11)
791 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addReg(X86::R11);
793 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp))
812 BuildMI(MBB, MBBI, DL, TII.get(getSUBrrOpcode(Uses64BitFramePtr)), SP)
830 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
866 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AndOp), Reg)
1088 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(MOVmr)), StackPtr, true, 16)
1110 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
1129 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
1137 TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr),
1153 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
1202 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
1217 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlign))
1251 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r))
1256 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1267 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1271 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri32), X86::RAX)
1275 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
1282 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1294 MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV64rm), X86::RAX),
1297 MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm), X86::EAX),
1308 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
1324 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), Establisher),
1331 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mr)), StackPtr,
1350 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), FramePtr),
1353 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rr), FramePtr)
1360 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
1378 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32mr)), FrameReg,
1390 if (unsigned Reg = TII.isStoreToStackSlot(FrameInstr, FI)) {
1402 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SaveXMM))
1412 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_EndPrologue))
1422 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mr)), StackPtr, false,
1449 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
1456 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)),
1472 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)), UsedReg, true, Offset)
1500 BuildMI(MBB, MBBI, DL, TII.get(X86::CLD))
1641 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::POP64r : X86::POP32r),
1702 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
1707 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
1729 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_Epilogue));
2106 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, getKillRegState(CanKill))
2126 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i - 1].getFrameIdx(), RC,
2149 BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), X86::RAX)
2157 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
2204 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
2215 BuildMI(MBB, MI, DL, TII.get(Opc), Reg)
2378 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
2381 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm)).addReg(ScratchReg)
2405 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
2410 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
2435 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
2438 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
2440 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
2447 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
2453 BuildMI(checkMBB, DL, TII.get(X86::JCC_1)).addMBB(&PrologueMBB).addImm(X86::COND_A);
2468 BuildMI(allocMBB, DL, TII.get(MOVrr), RegAX).addReg(Reg10);
2470 BuildMI(allocMBB, DL, TII.get(MOVri), Reg10)
2472 BuildMI(allocMBB, DL, TII.get(MOVri), Reg11)
2475 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
2477 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
2501 BuildMI(allocMBB, DL, TII.get(X86::CALL64m))
2510 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
2513 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
2518 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
2520 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
2690 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
2693 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
2695 BuildMI(stackCheckMBB, DL, TII.get(X86::JCC_1)).addMBB(&PrologueMBB).addImm(X86::COND_AE);
2698 BuildMI(incStackMBB, DL, TII.get(CALLop)).
2700 addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
2702 addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
2704 BuildMI(incStackMBB, DL, TII.get(X86::JCC_1)).addMBB(incStackMBB).addImm(X86::COND_LE);
2787 TII.get(STI.is64Bit() ? X86::POP64r : X86::POP32r), Regs[i]);
2797 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
2799 uint64_t Amount = TII.getFrameSize(*I);
2800 uint64_t InternalAmt = (isDestroy || Amount) ? TII.getFrameAdjustment(*I) : 0;
2966 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32rm), X86::ESP),
2979 BuildMI(MBB, MBBI, DL, TII.get(ADDri), FramePtr)
2989 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA32r), BasePtr),
2997 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32rm), FramePtr),
3222 addFrameReference(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mi32)),