|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
lib/Target/SystemZ/SystemZISelLowering.cpp 3553 if (VT.isVector()) {
3556 switch (VT.getScalarSizeInBits()) {
3560 Op = DAG.getNode(ISD::BITCAST, DL, VT, Op);
3562 SDValue Tmp = DAG.getNode(SystemZISD::VSHL_BY_SCALAR, DL, VT, Op, Shift);
3563 Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp);
3564 Op = DAG.getNode(SystemZISD::VSRL_BY_SCALAR, DL, VT, Op, Shift);
3570 Op = DAG.getNode(SystemZISD::VSUM, DL, VT, Op, Tmp);
3577 Op = DAG.getNode(SystemZISD::VSUM, DL, VT, Op, Tmp);
3590 return DAG.getConstant(0, DL, VT);
3593 int64_t OrigBitSize = VT.getSizeInBits();
3600 Op = DAG.getNode(ISD::TRUNCATE, DL, VT, Op);
3605 SDValue Tmp = DAG.getNode(ISD::SHL, DL, VT, Op, DAG.getConstant(I, DL, VT));
3605 SDValue Tmp = DAG.getNode(ISD::SHL, DL, VT, Op, DAG.getConstant(I, DL, VT));
3607 Tmp = DAG.getNode(ISD::AND, DL, VT, Tmp,
3608 DAG.getConstant(((uint64_t)1 << BitSize) - 1, DL, VT));
3609 Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp);
3614 Op = DAG.getNode(ISD::SRL, DL, VT, Op,
3615 DAG.getConstant(BitSize - 8, DL, VT));