reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
371 MachineFunction &MF = *MI.getParent()->getParent(); 374 if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMIo) 374 if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMIo) 375 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2); 382 if (MI.getOperand(3).getImm() != 0) 395 Register Reg0 = MI.getOperand(0).getReg(); 396 Register Reg1 = MI.getOperand(1).getReg(); 397 Register Reg2 = MI.getOperand(2).getReg(); 398 unsigned SubReg1 = MI.getOperand(1).getSubReg(); 399 unsigned SubReg2 = MI.getOperand(2).getSubReg(); 400 bool Reg1IsKill = MI.getOperand(1).isKill(); 401 bool Reg2IsKill = MI.getOperand(2).isKill(); 407 assert(MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) && 409 assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch"); 415 unsigned MB = MI.getOperand(4).getImm(); 416 unsigned ME = MI.getOperand(5).getImm(); 425 Register Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg(); 426 bool Reg0IsDead = MI.getOperand(0).isDead(); 427 return BuildMI(MF, MI.getDebugLoc(), MI.getDesc()) 427 return BuildMI(MF, MI.getDebugLoc(), MI.getDesc()) 436 MI.getOperand(0).setReg(Reg2); 437 MI.getOperand(0).setSubReg(SubReg2); 439 MI.getOperand(2).setReg(Reg1); 440 MI.getOperand(1).setReg(Reg2); 441 MI.getOperand(2).setSubReg(SubReg1); 442 MI.getOperand(1).setSubReg(SubReg2); 443 MI.getOperand(2).setIsKill(Reg1IsKill); 444 MI.getOperand(1).setIsKill(Reg2IsKill); 447 MI.getOperand(4).setImm((ME + 1) & 31); 448 MI.getOperand(5).setImm((MB - 1) & 31); 449 return &MI;