reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
13367 SDLoc dl(N); 13368 switch (N->getOpcode()) { 13371 return combineADD(N, DCI); 13373 return combineSHL(N, DCI); 13375 return combineSRA(N, DCI); 13377 return combineSRL(N, DCI); 13379 return combineMUL(N, DCI); 13381 if (isNullConstant(N->getOperand(0))) // 0 << V -> 0. 13382 return N->getOperand(0); 13385 if (isNullConstant(N->getOperand(0))) // 0 >>u V -> 0. 13386 return N->getOperand(0); 13389 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 13392 return N->getOperand(0); 13398 return DAGCombineExtBoolTrunc(N, DCI); 13400 return combineTRUNCATE(N, DCI); 13402 if (SDValue CSCC = combineSetCC(N, DCI)) 13406 return DAGCombineTruncBoolExt(N, DCI); 13409 return combineFPToIntToFP(N, DCI); 13411 if (ISD::isNormalLoad(N->getOperand(0).getNode())) { 13412 LSBaseSDNode* LSBase = cast<LSBaseSDNode>(N->getOperand(0)); 13413 return combineVReverseMemOP(cast<ShuffleVectorSDNode>(N), LSBase, DCI); 13418 EVT Op1VT = N->getOperand(1).getValueType(); 13419 unsigned Opcode = N->getOperand(1).getOpcode(); 13422 SDValue Val= combineStoreFPToInt(N, DCI); 13427 if (Opcode == ISD::VECTOR_SHUFFLE && ISD::isNormalStore(N)) { 13428 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N->getOperand(1)); 13429 SDValue Val= combineVReverseMemOP(SVN, cast<LSBaseSDNode>(N), DCI); 13435 if (cast<StoreSDNode>(N)->isUnindexed() && Opcode == ISD::BSWAP && 13436 N->getOperand(1).getNode()->hasOneUse() && 13442 EVT mVT = cast<StoreSDNode>(N)->getMemoryVT(); 13446 SDValue BSwapOp = N->getOperand(1).getOperand(0); 13463 N->getOperand(0), BSwapOp, N->getOperand(2), DAG.getValueType(mVT) 13463 N->getOperand(0), BSwapOp, N->getOperand(2), DAG.getValueType(mVT) 13467 Ops, cast<StoreSDNode>(N)->getMemoryVT(), 13468 cast<StoreSDNode>(N)->getMemOperand()); 13474 isa<ConstantSDNode>(N->getOperand(1)) && Op1VT == MVT::i32) { 13476 EVT MemVT = cast<StoreSDNode>(N)->getMemoryVT(); 13477 uint64_t Val64 = SignExtend64(N->getConstantOperandVal(1), 13484 DAG.UpdateNodeOperands(N, N->getOperand(0), Const64, N->getOperand(2), 13484 DAG.UpdateNodeOperands(N, N->getOperand(0), Const64, N->getOperand(2), 13484 DAG.UpdateNodeOperands(N, N->getOperand(0), Const64, N->getOperand(2), 13485 N->getOperand(3)); 13486 cast<StoreSDNode>(N)->setTruncatingStore(true); 13487 return SDValue(N, 0); 13497 return expandVSXStoreForLE(N, DCI); 13502 LoadSDNode *LD = cast<LoadSDNode>(N); 13512 return expandVSXLoadForLE(N, DCI); 13618 return SDValue(N, 0); 13626 ((Subtarget.hasAltivec() && ISD::isNON_EXTLoad(N) && 13761 DCI.CombineTo(N, Perm, TF); 13762 return SDValue(N, 0); 13768 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); 13774 N->getOperand(1)->getOpcode() == ISD::ADD) { 13775 SDValue Add = N->getOperand(1); 13826 SDValue V1 = N->getOperand(1); 13827 SDValue V2 = N->getOperand(2); 13859 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) { 13864 return expandVSXLoadForLE(N, DCI); 13872 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) { 13877 return expandVSXStoreForLE(N, DCI); 13883 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) && 13884 N->getOperand(0).hasOneUse() && 13885 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 || 13885 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 || 13887 N->getValueType(0) == MVT::i64))) { 13888 SDValue Load = N->getOperand(0); 13894 DAG.getValueType(N->getValueType(0)) // VT 13898 DAG.getVTList(N->getValueType(0) == MVT::i64 ? 13904 if (N->getValueType(0) == MVT::i16) 13909 DCI.CombineTo(N, ResVal); 13916 return SDValue(N, 0); 13924 if (!N->getOperand(0).hasOneUse() && 13925 !N->getOperand(1).hasOneUse() && 13926 !N->getOperand(2).hasOneUse()) { 13931 SDNode *LHSN = N->getOperand(0).getNode(); 13935 UI->getOperand(1) == N->getOperand(1) && 13936 UI->getOperand(2) == N->getOperand(2) && 13937 UI->getOperand(0) == N->getOperand(0)) { 13970 SDValue Cond = N->getOperand(1); 13971 SDValue Target = N->getOperand(2); 13984 N->getOperand(0), Target); 13993 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 13994 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3); 13994 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3); 14024 N->getOperand(0), N->getOperand(4)); 14024 N->getOperand(0), N->getOperand(4)); 14040 return N->getOperand(0); 14043 N->getOperand(0), N->getOperand(4)); 14043 N->getOperand(0), N->getOperand(4)); 14075 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0), 14078 N->getOperand(4), CompNode.getValue(1)); 14083 return DAGCombineBuildVector(N, DCI); 14085 return combineABS(N, DCI); 14087 return combineVSelect(N, DCI);