reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
10856 if (MI.getOpcode() == TargetOpcode::STACKMAP || 10857 MI.getOpcode() == TargetOpcode::PATCHPOINT) { 10859 MI.getOpcode() == TargetOpcode::PATCHPOINT) { 10865 MI.addOperand(MachineOperand::CreateReg(PPC::X2, false, true)); 10868 return emitPatchPoint(MI, BB); 10871 if (MI.getOpcode() == PPC::EH_SjLj_SetJmp32 || 10872 MI.getOpcode() == PPC::EH_SjLj_SetJmp64) { 10873 return emitEHSjLjSetJmp(MI, BB); 10874 } else if (MI.getOpcode() == PPC::EH_SjLj_LongJmp32 || 10875 MI.getOpcode() == PPC::EH_SjLj_LongJmp64) { 10876 return emitEHSjLjLongJmp(MI, BB); 10888 if (MI.getOpcode() == PPC::SELECT_CC_I4 || 10889 MI.getOpcode() == PPC::SELECT_CC_I8 || MI.getOpcode() == PPC::SELECT_I4 || 10889 MI.getOpcode() == PPC::SELECT_CC_I8 || MI.getOpcode() == PPC::SELECT_I4 || 10890 MI.getOpcode() == PPC::SELECT_I8) { 10892 if (MI.getOpcode() == PPC::SELECT_CC_I4 || 10893 MI.getOpcode() == PPC::SELECT_CC_I8) 10894 Cond.push_back(MI.getOperand(4)); 10897 Cond.push_back(MI.getOperand(1)); 10899 DebugLoc dl = MI.getDebugLoc(); 10900 TII->insertSelect(*BB, MI, dl, MI.getOperand(0).getReg(), Cond, 10900 TII->insertSelect(*BB, MI, dl, MI.getOperand(0).getReg(), Cond, 10901 MI.getOperand(2).getReg(), MI.getOperand(3).getReg()); 10901 MI.getOperand(2).getReg(), MI.getOperand(3).getReg()); 10902 } else if (MI.getOpcode() == PPC::SELECT_CC_I4 || 10903 MI.getOpcode() == PPC::SELECT_CC_I8 || 10904 MI.getOpcode() == PPC::SELECT_CC_F4 || 10905 MI.getOpcode() == PPC::SELECT_CC_F8 || 10906 MI.getOpcode() == PPC::SELECT_CC_F16 || 10907 MI.getOpcode() == PPC::SELECT_CC_QFRC || 10908 MI.getOpcode() == PPC::SELECT_CC_QSRC || 10909 MI.getOpcode() == PPC::SELECT_CC_QBRC || 10910 MI.getOpcode() == PPC::SELECT_CC_VRRC || 10911 MI.getOpcode() == PPC::SELECT_CC_VSFRC || 10912 MI.getOpcode() == PPC::SELECT_CC_VSSRC || 10913 MI.getOpcode() == PPC::SELECT_CC_VSRC || 10914 MI.getOpcode() == PPC::SELECT_CC_SPE4 || 10915 MI.getOpcode() == PPC::SELECT_CC_SPE || 10916 MI.getOpcode() == PPC::SELECT_I4 || 10917 MI.getOpcode() == PPC::SELECT_I8 || 10918 MI.getOpcode() == PPC::SELECT_F4 || 10919 MI.getOpcode() == PPC::SELECT_F8 || 10920 MI.getOpcode() == PPC::SELECT_F16 || 10921 MI.getOpcode() == PPC::SELECT_QFRC || 10922 MI.getOpcode() == PPC::SELECT_QSRC || 10923 MI.getOpcode() == PPC::SELECT_QBRC || 10924 MI.getOpcode() == PPC::SELECT_SPE || 10925 MI.getOpcode() == PPC::SELECT_SPE4 || 10926 MI.getOpcode() == PPC::SELECT_VRRC || 10927 MI.getOpcode() == PPC::SELECT_VSFRC || 10928 MI.getOpcode() == PPC::SELECT_VSSRC || 10929 MI.getOpcode() == PPC::SELECT_VSRC) { 10943 DebugLoc dl = MI.getDebugLoc(); 10949 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 10956 if (MI.getOpcode() == PPC::SELECT_I4 || MI.getOpcode() == PPC::SELECT_I8 || 10956 if (MI.getOpcode() == PPC::SELECT_I4 || MI.getOpcode() == PPC::SELECT_I8 || 10957 MI.getOpcode() == PPC::SELECT_F4 || MI.getOpcode() == PPC::SELECT_F8 || 10957 MI.getOpcode() == PPC::SELECT_F4 || MI.getOpcode() == PPC::SELECT_F8 || 10958 MI.getOpcode() == PPC::SELECT_F16 || 10959 MI.getOpcode() == PPC::SELECT_SPE4 || 10960 MI.getOpcode() == PPC::SELECT_SPE || 10961 MI.getOpcode() == PPC::SELECT_QFRC || 10962 MI.getOpcode() == PPC::SELECT_QSRC || 10963 MI.getOpcode() == PPC::SELECT_QBRC || 10964 MI.getOpcode() == PPC::SELECT_VRRC || 10965 MI.getOpcode() == PPC::SELECT_VSFRC || 10966 MI.getOpcode() == PPC::SELECT_VSSRC || 10967 MI.getOpcode() == PPC::SELECT_VSRC) { 10969 .addReg(MI.getOperand(1).getReg()) 10972 unsigned SelectPred = MI.getOperand(4).getImm(); 10975 .addReg(MI.getOperand(1).getReg()) 10991 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::PHI), MI.getOperand(0).getReg()) 10992 .addReg(MI.getOperand(3).getReg()) 10994 .addReg(MI.getOperand(2).getReg()) 10996 } else if (MI.getOpcode() == PPC::ReadTB) { 11011 DebugLoc dl = MI.getDebugLoc(); 11017 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 11025 Register LoReg = MI.getOperand(0).getReg(); 11026 Register HiReg = MI.getOperand(1).getReg(); 11044 } else if (MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I8) 11045 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4); 11046 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I16) 11047 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4); 11048 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I32) 11049 BB = EmitAtomicBinary(MI, BB, 4, PPC::ADD4); 11050 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I64) 11051 BB = EmitAtomicBinary(MI, BB, 8, PPC::ADD8); 11053 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I8) 11054 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND); 11055 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I16) 11056 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND); 11057 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I32) 11058 BB = EmitAtomicBinary(MI, BB, 4, PPC::AND); 11059 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I64) 11060 BB = EmitAtomicBinary(MI, BB, 8, PPC::AND8); 11062 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I8) 11063 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR); 11064 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I16) 11065 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR); 11066 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I32) 11067 BB = EmitAtomicBinary(MI, BB, 4, PPC::OR); 11068 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I64) 11069 BB = EmitAtomicBinary(MI, BB, 8, PPC::OR8); 11071 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I8) 11072 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR); 11073 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I16) 11074 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR); 11075 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I32) 11076 BB = EmitAtomicBinary(MI, BB, 4, PPC::XOR); 11077 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I64) 11078 BB = EmitAtomicBinary(MI, BB, 8, PPC::XOR8); 11080 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I8) 11081 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND); 11082 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I16) 11083 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND); 11084 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I32) 11085 BB = EmitAtomicBinary(MI, BB, 4, PPC::NAND); 11086 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I64) 11087 BB = EmitAtomicBinary(MI, BB, 8, PPC::NAND8); 11089 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I8) 11090 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF); 11091 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I16) 11092 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF); 11093 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I32) 11094 BB = EmitAtomicBinary(MI, BB, 4, PPC::SUBF); 11095 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I64) 11096 BB = EmitAtomicBinary(MI, BB, 8, PPC::SUBF8); 11098 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I8) 11099 BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPW, PPC::PRED_GE); 11100 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I16) 11101 BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPW, PPC::PRED_GE); 11102 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I32) 11103 BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPW, PPC::PRED_GE); 11104 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I64) 11105 BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPD, PPC::PRED_GE); 11107 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I8) 11108 BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPW, PPC::PRED_LE); 11109 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I16) 11110 BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPW, PPC::PRED_LE); 11111 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I32) 11112 BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPW, PPC::PRED_LE); 11113 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I64) 11114 BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPD, PPC::PRED_LE); 11116 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I8) 11117 BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPLW, PPC::PRED_GE); 11118 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I16) 11119 BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPLW, PPC::PRED_GE); 11120 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I32) 11121 BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPLW, PPC::PRED_GE); 11122 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I64) 11123 BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPLD, PPC::PRED_GE); 11125 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I8) 11126 BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPLW, PPC::PRED_LE); 11127 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I16) 11128 BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPLW, PPC::PRED_LE); 11129 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I32) 11130 BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPLW, PPC::PRED_LE); 11131 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I64) 11132 BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPLD, PPC::PRED_LE); 11134 else if (MI.getOpcode() == PPC::ATOMIC_SWAP_I8) 11135 BB = EmitPartwordAtomicBinary(MI, BB, true, 0); 11136 else if (MI.getOpcode() == PPC::ATOMIC_SWAP_I16) 11137 BB = EmitPartwordAtomicBinary(MI, BB, false, 0); 11138 else if (MI.getOpcode() == PPC::ATOMIC_SWAP_I32) 11139 BB = EmitAtomicBinary(MI, BB, 4, 0); 11140 else if (MI.getOpcode() == PPC::ATOMIC_SWAP_I64) 11141 BB = EmitAtomicBinary(MI, BB, 8, 0); 11142 else if (MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 || 11143 MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I64 || 11145 MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I8) || 11147 MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I16)) { 11148 bool is64bit = MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I64; 11152 switch (MI.getOpcode()) { 11174 Register dest = MI.getOperand(0).getReg(); 11175 Register ptrA = MI.getOperand(1).getReg(); 11176 Register ptrB = MI.getOperand(2).getReg(); 11177 Register oldval = MI.getOperand(3).getReg(); 11178 Register newval = MI.getOperand(4).getReg(); 11179 DebugLoc dl = MI.getDebugLoc(); 11190 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 11244 } else if (MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 || 11245 MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) { 11251 bool is8bit = MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I8; 11253 Register dest = MI.getOperand(0).getReg(); 11254 Register ptrA = MI.getOperand(1).getReg(); 11255 Register ptrB = MI.getOperand(2).getReg(); 11256 Register oldval = MI.getOperand(3).getReg(); 11257 Register newval = MI.getOperand(4).getReg(); 11258 DebugLoc dl = MI.getDebugLoc(); 11269 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 11430 } else if (MI.getOpcode() == PPC::FADDrtz) { 11434 Register Dest = MI.getOperand(0).getReg(); 11435 Register Src1 = MI.getOperand(1).getReg(); 11436 Register Src2 = MI.getOperand(2).getReg(); 11437 DebugLoc dl = MI.getDebugLoc(); 11443 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg); 11446 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31); 11447 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30); 11450 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2); 11453 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg); 11454 } else if (MI.getOpcode() == PPC::ANDIo_1_EQ_BIT || 11455 MI.getOpcode() == PPC::ANDIo_1_GT_BIT || 11456 MI.getOpcode() == PPC::ANDIo_1_EQ_BIT8 || 11457 MI.getOpcode() == PPC::ANDIo_1_GT_BIT8) { 11458 unsigned Opcode = (MI.getOpcode() == PPC::ANDIo_1_EQ_BIT8 || 11459 MI.getOpcode() == PPC::ANDIo_1_GT_BIT8) 11462 bool isEQ = (MI.getOpcode() == PPC::ANDIo_1_EQ_BIT || 11463 MI.getOpcode() == PPC::ANDIo_1_EQ_BIT8); 11469 DebugLoc dl = MI.getDebugLoc(); 11470 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest) 11471 .addReg(MI.getOperand(1).getReg()) 11473 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), 11474 MI.getOperand(0).getReg()) 11476 } else if (MI.getOpcode() == PPC::TCHECK_RET) { 11477 DebugLoc Dl = MI.getDebugLoc(); 11480 BuildMI(*BB, MI, Dl, TII->get(PPC::TCHECK), CRReg); 11481 BuildMI(*BB, MI, Dl, TII->get(TargetOpcode::COPY), 11482 MI.getOperand(0).getReg()) 11484 } else if (MI.getOpcode() == PPC::TBEGIN_RET) { 11485 DebugLoc Dl = MI.getDebugLoc(); 11486 unsigned Imm = MI.getOperand(1).getImm(); 11487 BuildMI(*BB, MI, Dl, TII->get(PPC::TBEGIN)).addImm(Imm); 11488 BuildMI(*BB, MI, Dl, TII->get(TargetOpcode::COPY), 11489 MI.getOperand(0).getReg()) 11491 } else if (MI.getOpcode() == PPC::SETRNDi) { 11492 DebugLoc dl = MI.getDebugLoc(); 11493 Register OldFPSCRReg = MI.getOperand(0).getReg(); 11496 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), OldFPSCRReg); 11507 unsigned Mode = MI.getOperand(1).getImm(); 11508 BuildMI(*BB, MI, dl, TII->get((Mode & 1) ? PPC::MTFSB1 : PPC::MTFSB0)) 11511 BuildMI(*BB, MI, dl, TII->get((Mode & 2) ? PPC::MTFSB1 : PPC::MTFSB0)) 11513 } else if (MI.getOpcode() == PPC::SETRND) { 11514 DebugLoc dl = MI.getDebugLoc(); 11523 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), DestReg) 11553 BuildMI(*BB, MI, dl, TII->get(StoreOp)) 11567 BuildMI(*BB, MI, dl, TII->get(LoadOp), DestReg) 11574 Register OldFPSCRReg = MI.getOperand(0).getReg(); 11577 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), OldFPSCRReg); 11587 MachineOperand SrcOp = MI.getOperand(1); 11599 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::IMPLICIT_DEF), ImDefReg); 11600 BuildMI(*BB, MI, dl, TII->get(PPC::INSERT_SUBREG), ExtSrcReg) 11606 BuildMI(*BB, MI, dl, TII->get(PPC::RLDIMI), NewFPSCRTmpReg) 11617 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)) 11626 MI.eraseFromParent(); // The pseudo instruction is gone now.